Design and implementation of asynchronous NOC architecture with buffer-less router

Patil, Trupti; Sandi, Anuradha M.

doi:10.1016/j.matpr.2021.05.282

Cited by 8 publications

(10 citation statements)

References 9 publications

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“…This article only discusses a network-on-a-chip using asynchronous routers. Some papers refer to distributed synchronous networks as GAL's systems [2], [18], but these networks do not directly use Asynchronous circuits, which is inconsistent with the Asynchronous circuit-based NoC concept discussed in this paper.…”

Section: Synchronous and Asynchronous Interface Designmentioning

confidence: 74%

“…The increase in the area is due to the increase in the data depth, data width, and circuit for clock recovery. There is a power reduction of 5 times compared to [18] and 2 times compared to [2] and 9 times compared to [25] as shown in Table 1 and in fig. 12-15.…”

Section: Resultsmentioning

confidence: 93%

“…In the proposed architecture, 2D 4x4 Asynchronous Mesh NoC architecture with a data size of 64-bits and depth of 64 is proposed. When compared with the research article cited in [2], [18], and [25], the proposed design shows better performance in terms of area and power. The increase in the area is due to the increase in the data depth, data width, and circuit for clock recovery.…”

Section: Resultsmentioning

confidence: 93%

“…Out of this 23.64%, 20.93% is occupied by the Flip Flop and the rest 2.71% is occupied by the Latches. The research work reported in the [18], 2D 4x4 Asynchronous Mesh NoC architecture with a data size of 48-bits and depth of 5 is proposed. In the proposed architecture, 2D 4x4 Asynchronous Mesh NoC architecture with a data size of 64-bits and depth of 64 is proposed.…”

Section: Resultsmentioning

confidence: 99%

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Design and Development of Low Power Clock and Data Recovery Circuit for Asynchronous Network on Chips

Nagalaxmi

Rao²,

P.Chandrasekar

2022

JICS

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Today, the current buffered router Synchronous Network on Chip architecture consumes significant chip area and power. Therefore, based on biased routing, buffer-less routers have recently been predicted as a possible solution, but they suffer from contiguous port assignments, slow critical paths, and increased latency. Asynchronous Network on Chip architecture emerges as the best option for avoiding glitches and consuming less power. A clock and data recovery circuit is used to recover the clock signal from the router-generated data and reduce power consumption in a Multiprocessor System on Chip. This paper proposes a clock and data recovery circuit design for an asynchronous Network on Chip. The proposed 4x4 Mesh router architecture implemented in this paper can process 64-bit of data samples with a depth of 64. When comparing the proposed architecture with the existing NoC architecture, the proposed architecture has shown a power reduction of 5times. The proposed architecture has consumed a total power of 0.103W.

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Section: Synchronous and Asynchronous Interface Designmentioning

confidence: 74%

Section: Resultsmentioning

confidence: 93%

Section: Resultsmentioning

confidence: 93%

Section: Resultsmentioning

confidence: 99%

See 2 more Smart Citations

Design and Development of Low Power Clock and Data Recovery Circuit for Asynchronous Network on Chips

Nagalaxmi

Rao²,

P.Chandrasekar

2022

JICS

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“…Upon the transmission of a routing request signal from the processing meta-cluster, the data packet is placed into the dynamic buffer, awaiting the router's allocation of the routing path. Moving on to the performance analysis of the shunt router, Table 1 presents a comparison of hardware resource utilization between the offload router designed in this study and the on-chip hybrid router proposed in [17][18][19]. Our router utilizes 65.9% fewer register resources and 65.1% fewer LUT resources than the router in [19].…”

Section: Electric Router Structurementioning

confidence: 99%

Design and Implementation of Reconfigurable Array Adaptive Optoelectronic Hybrid Interconnect Shunting Network

Yang,

Li,

et al. 2024

Electronics

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Addressing challenges regarding Hybrid Optoelectronic Network-on-Chip systems, such as congestion control, their limited adaptability, and their inability to facilitate optoelectronic co-simulation, this study introduces an adaptive hybrid optoelectronic interconnection shunt structure tailored for reconfigurable array processors. Within this framework, an adaptive shunt routing algorithm and a low-loss non-blocking five-port optical router are developed. Furthermore, an adaptive hybrid optoelectronic interconnection simulation model and a performance statistical model, established using SystemVerilog and Verilog, complement these designs. The experimental results showcase promising enhancements: the designed routing algorithm demonstrates an average 17.5% improvement in mitigating congestion at network edge nodes; substantial reductions in the required number of cross waveguides and micro-ring resonators for optical routers lead to an average path insertion loss of only 0.522 dB. Moreover, the hybrid optoelectronic interconnection performance statistical model supports the design of routing strategies and topology structures, enabling resource usage, power consumption, insertion loss, and other performance metrics to be accurately assessed.

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Design and implementation of network‐on‐chip router using multi‐priority based iterative round‐robin matching with slip

Singh

Ravindra²,

Naik

2022

Trans Emerging Tel Tech

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Nowadays, network‐on‐chip (NoC) routers become important in several applications including mobile technology and digital communication. Multiple cores/processors are typically coupled using NoC routers, which considerably improve integrated circuit performance in terms of power, latency, throughput, and area. So, a novel 4 × 4 topology‐based NoC router using multi‐priority based iterative round‐robin matching with slip (MPiSLIP) routing algorithm is implemented in this work. The proposed work contains different operational blocks classification such as route computation using static straight allocator, route controlling using MPiSLIP arbiter, a crossbar switch, combined parallel virtual channel and switch allocation unit, look ahead bypass route computation (LBRC), and input‐output ports. The MPiSLIP routing mechanism also determines the priorities necessary for route development. Finally, by bypassing the switches and fulfilling all of the priories in a look‐ahead manner, LBRC is employed to establish the effective path between input ports and output ports. The simulation results show that the proposed MPiSLIP‐based NoC routing method resulted in a reduced area, power, and latency as compared to the open‐source NoCs, multi‐processor NoCs, multi‐core NoCs, and conventional routing algorithms.

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Design and implementation of asynchronous NOC architecture with buffer-less router

Cited by 8 publications

References 9 publications

Design and Development of Low Power Clock and Data Recovery Circuit for Asynchronous Network on Chips

Design and Development of Low Power Clock and Data Recovery Circuit for Asynchronous Network on Chips

Design and Implementation of Reconfigurable Array Adaptive Optoelectronic Hybrid Interconnect Shunting Network

Design and implementation of network‐on‐chip router using multi‐priority based iterative round‐robin matching with slip

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