Design and implementation of area-efficient DVB-S2 BCH decoder

Zhang, Botao; Liu, Dongpei; Wang, Shixian; Chen, Xucan; Liu, Hengzhu

doi:10.1109/iccet.2010.5485823

Cited by 1 publication

(3 citation statements)

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“…In all three units in the upper part of Figure 1, FFMs are the key components (Chen et al, 2009) (Zhang et al, 2010). However, the complexity of some FFMs can be reduced at design time, since they have one input fixed to a constant value out of the specific Galois field used.…”

Section: Bch Decoder Architecturementioning

confidence: 99%

“…In all three units in the upper part of Fig. 1, FFMs are the key components (Chen et al, 2009;Zhang et al, 2010).…”

Section: Bch Decoder Architecturementioning

confidence: 99%

“…However, the specific FFM requirements vary over the application range: high Galois field dimensions are used in cryptography, whereas for FFMs in channel coding the focus lies on high throughput and low latency. FFMs are key components in BCH decoder implementations and consume a significant amount of hardware resources in the overall design (Chen et al, 2009;Zhang et al, 2010).…”

Section: Introductionmentioning

confidence: 99%

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Design space exploration of high throughput finite field multipliers for channel coding on Xilinx FPGAs

et al. 2012

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Channel coding is a standard technique in all wireless communication systems. In addition to the typically employed methods like convolutional coding, turbo coding or low density parity check (LDPC) coding, algebraic codes are used in many cases. For example, outer BCH coding is applied in the DVB-S2 standard for satellite TV broadcasting. A key operation for BCH and the related Reed-Solomon codes are multiplications in finite fields (Galois Fields), where extension fields of prime fields are used. A lot of architectures for multiplications in finite fields have been published over the last decades. This paper examines four different multiplier architectures in detail that offer the potential for very high throughputs. We investigate the implementation performance of these multipliers on FPGA technology in the context of channel coding. We study the efficiency of the multipliers with respect to area, frequency and throughput, as well as configurability and scalability. The implementation data of the fully verified circuits are provided for a Xilinx Virtex-4 device after place and route.Published by Copernicus Publications on behalf of the URSI Landesausschuss in der Bundesrepublik Deutschland e.V.

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Section: Bch Decoder Architecturementioning

confidence: 99%

“…In all three units in the upper part of Fig. 1, FFMs are the key components (Chen et al, 2009;Zhang et al, 2010).…”

Section: Bch Decoder Architecturementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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