Design and Implementation of Adders using Novel Reversible Gates in Quantum Cellular Automata

Kamaraj, A.; Marichamy, P.; Devi, S. Karthika; Subraja, M. Nagalakshmi

doi:10.17485/ijst/2016/v9i8/87929

Cited by 5 publications

(1 citation statement)

References 6 publications

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“…[9]. Here the input of the control signal is varied as either Adder/Subtractor where a single unit can be either used as Adder or Subtractor.…”

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confidence: 99%

Design of Parity Preserving Reversible DIF-FFT using 90nm Technology

F.¹,

Aishwarya²

2019

IJEAT

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Reduction of power consumption is the major goal in modern circuit design. Reversible logic gate do not lose any information & thus have zero power dissipation. In all signal processing applications, the most important computation involved is Fast Fourier Transform (FFT). For the fault tolerance computation parity preserving logic can be used .The authors present an efficient parity preserving reversible DIF-FFT using 90nm technology. The implementation involves the design of DIF-FFT with reversible P2RG along with Fredkin gate over different combinations of adders (Carry look ahead adder (CLA), Carry save adders (CSA), Carry skip adder (CSK) & Ripple carry adder (RCA)) & multipliers (Array Multiplier (AM), Carry Save Multiplier (CM), Parallel Multiplier (PM), Wallace Tree Multiplier (WM)). DIF-FFT Architectures of different combinations were coded using Verilog & the same was simulated by Modelsim 6.3f. Parameters such as Hardware Device utilization & Power analysis were done using Quartus II 9.0 with respect to Stratix II device which works on 90nm technology. It was found that DIF-FFT Architecture designed using CSA & CM uses lesser resource utilization whereas architecture designed using CSA & AM has lesser Power dissipation by 72% & 81% respectively.

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“…[9]. Here the input of the control signal is varied as either Adder/Subtractor where a single unit can be either used as Adder or Subtractor.…”

mentioning

confidence: 99%