Design and Implementation of a Smart Automated OUT-ward (SAT OUT) System Using ARM Processor for Aircrafts

Kushal, K. S.; Chetan, S; Shivaputra,

doi:10.1109/cicn.2012.83

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2016

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“…namely IEEE1149.1 standard. This specification provides a complete and standardized method of testable design [4] , so it gets the support of the world's most integrated circuit manufacturers and test contractor, such as ARM Company's ARM7TDMI processor [5] , Xilinx company's series of FPGA above XC3000.…”

Section: Introductionmentioning

confidence: 99%

A Testable Design Method for Memories by Boundary Scan Technique

et al. 2016

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This paper presents a design for test the embedded flash in an object System-on-a-chip (SoC). The feature of the Flash TAP (Test Access Port) complies with the IEEE std.1149.1, and it can select different scan chains and other control registers for other test. By the trade-off between the test time and the circuit area, an IST (In System Test) circuit is designed in the SoC. Experiment results on the embedded memory have shown that the proposed method costs small testing timing by the use of IST.

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Section: Introductionmentioning

confidence: 99%