Design and implementation of a digital down/up conversion directly from/to RF channels in HDL

Motta, Lucas L.; Acurio, Byron Alejandro Acuña; Aniceto, Nathália Figueiredo Tinoco; Meloni, Luís Geraldo Pedroso

doi:10.1016/j.vlsi.2019.05.006

Cited by 12 publications

(3 citation statements)

References 2 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…For example, the input data is P (8, 7), and the coefficient data is A (3,12). Hence, the multiplication and accumulation data are P (12,19) and P (14,19) respectively [for R1 = 4].…”

Section: Data Truncationmentioning

confidence: 99%

“…In the last decade, several researchers have reported hardware-efficient different DDC architectures on FPGA devices. Recently, the authors in L. L. Motta et al [3] have proposed a digital up-down converter using polyphase cascaded integrated comb (CIC) filters. The simulation results show the functional verification of the filters, and the design has achieved a high performance using fixed-point filter coefficients.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Area and power-efficient reconfigurable digital down converter on FPGA

Datta

Dutta

2022

FACTA U EE

View full text Add to dashboard Cite

This paper presents a field-programmable gate array (FPGA)-based digital down converter (DDC) that can reduce the bandwidth from about 70 MHz to 182.292 kHz. The proposed DDC consists of a polyphase COordinate Rotation DIgital Computer (CORDIC) processor and a multirate filter. The advantage of polyphase CORDIC processor is to process with high sample rate input data and produces computational efficient noiseless baseband spectrum. The pipeline multirate filter works at a high clock speed. Moreover, the multirate filter generates a fractional sample rate factor using a cubic B-spline Farrow filter. The proposed DDC is coded with optimal hardware description language (HDL) and tested on Kintex-7 Xilinx FPGA as the target device. Experimental results indicate that the proposed design saves chip area, power consumption and operates at high speed without loss of any functionality. Additionally, the proposed design offers sufficient spurious-free dynamic range (SFDR) and produces less than 1 Hz frequency resolution at the output.

show abstract

“…For example, the input data is P (8, 7), and the coefficient data is A (3,12). Hence, the multiplication and accumulation data are P (12,19) and P (14,19) respectively [for R1 = 4].…”

Section: Data Truncationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Area and power-efficient reconfigurable digital down converter on FPGA

Datta

Dutta

2022

FACTA U EE

View full text Add to dashboard Cite

show abstract

“…Processing such high-bandwidth signals may push traditional electronic methods to their thresholds. One approach to deal with this issue involves down-converting the high-bandwidth signal 8,9 into parallel low-bandwidth signals, followed by processing these signals with low-bandwidth electronics. Overall, it is feasible to perform high-bandwidth signal measurements with a variety of sampling techniques utilizing electrical samplers, such as electrical sample-and-hold circuits or optical samplers.…”

Section: Introductionmentioning

confidence: 99%