Design and implementation of a new architecture of a real‐time reconfigurable digital modulator on FPGA

Abstract

One of the prerequisites of electronic warfare (EW) is to have the means to provide secure point-to-point wireless data and voice communications with other ground stations. New technologies are giving rise to bigger information security threats. This situation illustrates the best the urgency of reducing the development time of EW systems. Previous works suggest that digital systems are the best candidates for this purpose and therefore form the backbone of modern EW. As a result, digital modulation techniques are widely used in modern wireless communication systems. This is largely due to their high resistance to noise and their high transmission capacity that can be achieved through data multiplexing. In this Letter, a new reconfigurable architecture of a phase shift keying (PSK) modulator is described and implemented on FPGA. The latter can be configured in real time to produce the following modulation schemes: QPSK, 8-PSK, and 16-PSK without having to regenerate the FPGA configuration bits. This action can be done by software via programming or manually using a DIP switch. The proposed design is implemented on the Xilinx xc7k325tfbg900 FPGA using the Genesis 2 development board. The experimental results are in agreement with the simulations.

A Survey on Vital Signs Detection Using Radar Techniques and Processing With FPGA Implementation

“…The classification of literature based on the processing platform is particularly useful when determining specific platforms for the implementation of different algorithms. [20], [22], [23], [25], [26], [28], [37], [35], [7], [38], [39], [55], [56], [57], [70], [71] FPGA [2], [21], [31], [54], [40], [43], [44], [45], [49], [62], [72], [73], [74], [75], [76] FPGA (not specifically for vital sign detection) [52], [53], [68], [77], [78], [79], [80], [81], [82], [83], [84] SoC [42] DSP [30] FPGA-GPU [69] PC-microcontroller [29], [27] DSP-microcontroller…”

“…This implementation achieved a processing delay of around 2.569 ns. Besides that, reconfigurable phase shift keying was synthesized using FPGA in reference [79].…”