Design and implementation of a hybrid DPWM under 50 ps resolution based on general‐purpose FPGA

Abstract

SummaryHigh‐resolution pulse width modulators are used widely in different fields of electrical engineering, such as dimming of light‐emitting diode (LED) lighting, motor control, RF modulators, audio amplifiers, and switch‐mode power supplies. To realize a high‐resolution digital pulse‐width modulator (DPWM) in a limited inner system clock, a simple implementation of a hybrid DPWM with the resolution under 50 ps based on a general‐purpose field‐programmable gate array (FPGA) is described. The multiplexer device implementing the fast carry‐chain path and an AND gate controlling the selection input are used as a delay unit. The manual routing or placement is not required in the proposed approach, which just needs some conditional constraints. Some different conditional constraints influencing the monotonicity and resolution of DPWM are discussed. Finally, a 1 MHz switching frequency DPWM with 40 ps resolution is experimentally demonstrated, with high monotonicity and linearity. Further, a synchronous buck with and without this high‐resolution DPWM is experimentally compared to illustrate the regulation resolution.

Multiphase digital integration constant on‐time–controlled Buck converter with high‐resolution current balance scheme for ultrafast load transient

“…By considering the mismatch device trace, 4 carry chain multiplexers are used as a delay cell to realize the resolution of 40 ps. 21 The schematic of a single-delay cell is also shown in Figure 25. Recall the transfer function in (4), and the minimum time variation τ is reduced to 40 ps by applying the delay line structure.…”

“…In Xilinx Kintex7325t FPGA implementation, the delay of a single carry chain multiplexer is approximately 10 ps. By considering the mismatch device trace, 4 carry chain multiplexers are used as a delay cell to realize the resolution of 40 ps 21 . The schematic of a single‐delay cell is also shown in Figure 25.…”

“…However, the COT current balance scheme in Chen et al 19 is analog and does not have a resolution issue. The delayline-based structures proposed in the previous studies [21][22][23][24][25] are widely used in digital control to improve the digital PWM (DPWM) resolution in PWM-controlled converters. However, it is needed a new high-resolution structure to improve the existing T ON generator of COT control to enhance the resolution of current balance.…”

Design and Implementation of Two Hybrid High Frequency DPWMs Using Delay Blocks on FPGAs

“…Otra arquitectura híbrida es la que se presenta en [23], en ella los autores utilizan una línea de retardos que cuyo diseño está formado por un camino de cadena de arrastre, una puerta AND y un bloque Set-Reset para ajustar el retardo deseado. Para este diseño se emplearon una serie de directivas en el rutado para evitar tener que hacer el rutado manual, logrando una resolución de tiempo igual a 40,2 ps generando una señal PWM de 1 MHz.…”