Design and implementation of a versatile cryptographic unit for RISC processors

Yumbul, Kazim; Savaş, Erkay; Kocabaş, Övünç; Groβschädl, Johann

doi:10.1002/sec.555

Cited by 3 publications

(7 citation statements)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…This way, a wider range of public key algorithms based on modular arithmetic can be protected against fault attacks. The cost of integrating non-linear arithmetic error-correcting codes in embedded processors is evaluated in [57,60]. Detecting capability and design choices of the error correcting codes against an intelligent and powerful attacker are discussed in detail in [59].…”

Section: Feasibility Of Fault Attacks and Countermeasuresmentioning

confidence: 99%

Attacks on implementations of cryptographic algorithms

Savaş

2013

Proceedings of the 6th International Conference on Security of Information and Networks

Self Cite

View full text Add to dashboard Cite

Cryptographic algorithms, which withstand cryptanalysis after years of rigorous theoretical study and detailed scrutiny have been shown to succumb to attacks that exploit the vulnerabilities in their implementations. Therefore, there has been a vast amount of research effort to find potential vulnerabilities in the implementation of cryptographic algorithms, and efficient and effective countermeasures if such vulnerabilities exist. In this paper, we survey side-channel and fault attacks, which are two powerful methods that have been demonstrated to render many implementations effectively broken. While we categorically analyze the attack techniques, possible countermeasures will also be discussed.

show abstract

Section: Feasibility Of Fault Attacks and Countermeasuresmentioning

confidence: 99%

Attacks on implementations of cryptographic algorithms

Savaş

2013

Proceedings of the 6th International Conference on Security of Information and Networks

Self Cite

View full text Add to dashboard Cite

show abstract

“…Any data that goes out of the chip Other architectures modify or extend processor cores mostly for accelerating the cryptographic algorithms [23], [24]. There are also other architectures, which propose solutions for both secure and fast execution of cryptographic algorithms [19], [21], [1] and [20]. A recent work in [24] explores design possibilities for accelerating cryptographic algorithms while secure execution is not considered.…”

Section: Related Work and Our Contributionmentioning

confidence: 99%

“…The implementation of instructions for efficient integer and logic operations has been explained in detail in our previous works [19,20]. Therefore, we focus only on explaining the new instructions that allow secure execution of cryptographic operations; but only a subset of new instructions, which we think are the most representative of the adopted methodology, is explained for space considerations.…”

Section: The New Instruction Set Architecturementioning

confidence: 99%

“…The protected zone consists of architectural subsystems of a local memory, registers, and functional units and enables a much more strict process isolation in the sense that sensitive information never leaks outside the zone. For acceleration of basic arithmetic operations, we use and improve the design principles presented in [19,20]. The goal of accelerating many cryptographic algorithms (AES, hash functions, elliptic curve cryptography, RSA, Pairing-based cryptography) has a major influence on the design of the functional units and the organization of the protected zone.…”

mentioning

confidence: 99%

See 1 more Smart Citation

Enhancing an Embedded Processor Core for Efficient and Isolated Execution of Cryptographic Algorithms^†

Yumbul

Savaş

2014

The Computer Journal

Self Cite

View full text Add to dashboard Cite

We propose enhancing a reconfigurable and extensible embedded RISC processor core with a protected zone for isolated execution of cryptographic algorithms. The protected zone is a collection of processor subsystems such as functional units optimized for high-speed execution of integer operations, a small amount of local memory for storing sensitive data during cryptographic computations, and special-purpose and cryptographic registers to execute instructions securely. We outline the principles for secure software implementations of cryptographic algorithms in a processor equipped with the proposed protected zone. We demonstrate the efficiency and effectiveness of our proposed zone by implementing the most-commonly used cryptographic algorithms in the protected zone; namely RSA, elliptic curve cryptography, pairing-based cryptography, AES block cipher, and SHA-1 and SHA-256 cryptographic hash functions. In terms of time efficiency, our software implementations of cryptographic algorithms running on the enhanced core compare favorably with equivalent software implementations on similar processors reported in the literature. The protected zone is designed in such a modular fashion that it can easily be integrated into any RISC processor. The proposed enhancements for the protected * Preliminary version of this paper has been presented at Reconfig 2009 [1]. zone are realized on an FPGA device. The implementation results on the FPGA confirm that its area overhead is relatively moderate in the sense that it can be used in many embedded processors. Finally, the protected zone is useful against cold-boot and micro-architectural sidechannel attacks such as cache-based and branch prediction attacks.

show abstract

“…This method reduces the time consumption of round function significantly and is the fastest non-parallelised software implementation which has been adopted by many security systems like OpenSSL (Viega et al, 2002). Moreover, the LUT-based AES software implementations are more applicable than the ones based on hardware accelerators (Rahimunnisa et al, 2014;Abdellatif et al, 2014;Chang et al, 2013;Swankoski et al, 2005) or the ones based on instruction set extension (Rott, 2012;Lee and Chen, 2010;Yumbul et al, 2014) due to its' hardware-independency characteristic.…”

Section: Introductionmentioning

confidence: 99%

Access-driven cache attack resistant and fast AES implementation

Wan

Luo

et al. 2018

IJES

View full text Add to dashboard Cite

Contents:IJES is a refereed international journal providing an international forum to report, discuss and exchange experimental or theoretical results, novel designs, work-in-progress, experience, case studies, and trend-setting ideas. Papers should be of a quality that represents the latest advances in embedded systems in time-to-market, cost, code size, weight, testability, power, real-time behaviour, and stimulating future trends.

show abstract

Design and implementation of a versatile cryptographic unit for RISC processors

Cited by 3 publications

References 11 publications

Attacks on implementations of cryptographic algorithms

Attacks on implementations of cryptographic algorithms

Enhancing an Embedded Processor Core for Efficient and Isolated Execution of Cryptographic Algorithms^†

Access-driven cache attack resistant and fast AES implementation

Contact Info

Product

Resources

About

Design and implementation of a versatile cryptographic unit for RISC processors

Cited by 3 publications

References 11 publications

Attacks on implementations of cryptographic algorithms

Attacks on implementations of cryptographic algorithms

Enhancing an Embedded Processor Core for Efficient and Isolated Execution of Cryptographic Algorithms†

Access-driven cache attack resistant and fast AES implementation

Contact Info

Product

Resources

About

Enhancing an Embedded Processor Core for Efficient and Isolated Execution of Cryptographic Algorithms^†