Design and Implementation of a Novel Complete Filter for EEG Application on FPGA

Mahabub, Atik

doi:10.5815/ijigsp.2018.06.03

“…This comparison of time complexities and hardware of proposed DA-FIR designs with other filter designs is as depicted in Table 5. The Table 4 illustrates our best solution and compares the obtained parameters of our synthesis results with previous works in terms of numerical values of (MSP)-Minimum Sampling Period(ns), Area(μm 2 ), Power(mw) ,(ADP)-Area Delay Product(μm 2 ns), Energy per output, Throughput(MHz) [29,30]. Further the Table 5 compares the obtained results in our work with previous works with numerically addressing with mathematical formulas of various parameters such as Throughput, multipliers, adders and registers [31,32].…”

Section: Resultsmentioning

confidence: 99%

Design and implementation of DA FIR filter for bio-inspired computing architecture

Prashanth

¹

,

Ahmed

²

,

Kounte

³

2021

IJECE

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This paper elucidates the system construct of DA-FIR filter optimized for design of distributed arithmetic (DA) finite impulse response (FIR) filter and is based on architecture with tightly coupled co-processor based data processing units. With a series of look-up-table (LUT) accesses in order to emulate multiply and accumulate operations the constructed DA based FIR filter is implemented on FPGA. The very high speed integrated circuit hardware description language (VHDL) is used implement the proposed filter and the design is verified using simulation. This paper discusses two optimization algorithms and resulting optimizations are incorporated into LUT layer and architecture extractions. The proposed method offers an optimized design in the form of offers average miminimizations of the number of LUT, reduction in populated slices and gate minimization for DA-finite impulse response filter. This research paves a direction towards development of bio inspired computing architectures developed without logically intensive operations, obtaining the desired specifications with respect to performance, timing, and reliability.

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“…In (Dutande et al 2018), author proposed a low pass butterworth filter for removing out-band components and adaptive LMS noise canceller for removing in-band components from EEG data signal. In (Mahabub 2018), author proposed a complete filter which is a combination of integrator filter and differentiate filter which support detection of both low and high noises. The total FPGA utilization for complete filter is less than 1%.…”

Section: Related Workmentioning

confidence: 99%

A Flexible Software-Hardware Framework for Brain EEG Multiple Artifact Identification

Khatwani

¹

,

Rashid

²

,

Paneliya

³

et al. 2022

Handbook of Biochips

0

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Our proposed network achieves 93.14% classification accuracy using EEG dataset collected by a 64 channel BioSemi ActiveTwo headsets, averaged across 17 patients and 10 artifact classes. Our hardware architecture is fully parameterized with number of input channels, filters, depth and data bit-width. The number of processing engines (PE) in the proposed hardware can vary between 1 to 16 providing different latency, throughput, power and energy efficiency measurements. We implement our custom hardware architecture on Xilinx FPGA (Artix-7) which on average consumes 1.4 mJ to 4.7 mJ dynamic energy with different PE configurations. Energy consumption is further reduced by 16.7× implementing on application-specified integrated circuit at the post layout level in 65-nm CMOS technology. Our FPGA implementation is 1.7× to 5.15× higher energy efficient than some previous works. Moreover, our ASIC implementation is also 8.47× to 25.79× higher energy efficient compared to previous works. We also demonstrated that the proposed network is reconfigurable to detect artifacts from another EEG dataset collected in our lab by a 14 channel Emotiv EPOC+ headset and achieved 93.5% accuracy for eye blink artifact detection.

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A Flexible Software-Hardware Framework for Brain EEG Multiple Artifact Identification

Khatwani¹,

Rashid²,

Paneliya³

et al. 2021

Handbook of Biochips

0

View full text Add to dashboard Cite

Our proposed network achieves 93.14% classification accuracy using EEG dataset collected by a 64 channel BioSemi ActiveTwo headsets, averaged across 17 patients and 10 artifact classes. Our hardware architecture is fully parameterized with number of input channels, filters, depth and data bit-width. The number of processing engines (PE) in the proposed hardware can vary between 1 to 16 providing different latency, throughput, power and energy efficiency measurements. We implement our custom hardware architecture on Xilinx FPGA (Artix-7) which on average consumes 1.4 mJ to 4.7 mJ dynamic energy with different PE configurations. Energy consumption is further reduced by 16.7× implementing on application-specified integrated circuit at the post layout level in 65-nm CMOS technology. Our FPGA implementation is 1.7× to 5.15× higher energy efficient than some previous works. Moreover, our ASIC implementation is also 8.47× to 25.79× higher energy efficient compared to previous works. We also demonstrated that the proposed network is reconfigurable to detect artifacts from another EEG dataset collected in our lab by a 14 channel Emotiv EPOC+ headset and achieved 93.5% accuracy for eye blink artifact detection.

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Design and Implementation of a Novel Complete Filter for EEG Application on FPGA

Cited by 5 publications

References 7 publications

Design and implementation of DA FIR filter for bio-inspired computing architecture

Design and implementation of DA FIR filter for bio-inspired computing architecture

A Flexible Software-Hardware Framework for Brain EEG Multiple Artifact Identification

A Flexible Software-Hardware Framework for Brain EEG Multiple Artifact Identification

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