Design and Implementation of a 50MHZ DXT CoProcessor

Amiri,; Atani,; Mirzakuchaki, Sattar; Mahdavi, Mojdeh

doi:10.1109/dsd.2007.4341448

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2008

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“…Several algorithms and implementations have been proposed for the DXTs, spreading from software implementations in DSPs to hardware implementations in ASICs ( [1], [2], [3], [7], and [10]). The DXTs are computationally intensive and as such, there is a great demand for high speed, high throughput and short latency computing architectures.…”

Section: Introductionmentioning

confidence: 99%

Design and Implementation of an Image CoProcessor

Atani¹,

Mirzakuchaki²,

Atani

2008

Lecture Notes in Computer Science

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Abstract. This paper presents a novel DA based 2D DCT/DST coprocessor architecture for the synchronous design in a Xilinx FPGA device. A 1.2V, 90nm triple-oxide technology, Virtex-IV FPGA is used for final implementation and maximum operating frequency of 117 MHz is achieved. Using XPower toolbox, the total dynamic power consumption of 393 mW is measured. The paper presents the trade-offs involved in designing the architecture, and the design for performance issues.

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