Design and Implementation of a Low-power Baseband-system for RFID Tag

Man, A.S.W.; Zhang, E.S.; Chan, Hin-Tat; Lau, V.K.N.; Tsui, Chi-Ying; Luong, Howard C.

doi:10.1109/iscas.2007.378716

Cited by 31 publications

(14 citation statements)

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“…Even though there are some works in the literature that work at 1.92MHz, such as (Wang et al, 2007), most works propose digital cores for other clock frequencies. For example, (Hong et al, 2008) works at 4 MHz, (Man et al, 2007) at 3.3MHz, (Zhang et al , 2008;Yan et al, 2006) at 1.28MHz and (Ricci et al, 2008) at 2MHz. A study of the constraints on the clock signal of the digital core is needed so that the clock frequency can be optimally selected.…”

Section: Input Power In the Tagmentioning

confidence: 99%

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Design Considerations for the Digital Core of a C1G2 RFID Tag

Zalbide¹,

Sevillano²,

Vélez³

2010

Radio Frequency Identification Fundamentals and Applications Design Methods and Solutions

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Section: Input Power In the Tagmentioning

confidence: 99%

“…Almost every recent research work concerning passive long range UHF RFID tags uses this communication protocol; e.g. : (Yan et al, 2006;Barnett et al 2007;Man et al, 2007;Ricci et al, 2008;Zhang et al, 2008;Roostaie et al 2008;Wanggen et al 2009). Thus, this chapter is focused in the C1G2 standard.…”

Section: Introductionmentioning

confidence: 99%

Design Considerations for the Digital Core of a C1G2 RFID Tag

Zalbide¹,

Sevillano²,

Vélez³

2010

Radio Frequency Identification Fundamentals and Applications Design Methods and Solutions

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“…While, the comparator interprets subsequent interrogator symbols shorter than pivot to be data-0s, and subsequent interrogator symbols longer than pivot to be data-1s [2]. Unfortunately, the scheme presented above requires too much power due to their high frequency operation [5,6]. Usually, through measuring the length of TRcal and extracting the information of DR, the baseband processor divides the clock and generates a discrete BLF, which is different from the continuous BLF demanded in Eq.…”

Section: Conventional Architecturementioning

confidence: 99%

A clock-free decoder and continuous BLF generator for EPCglobal Gen2 UHF RFID tags

Tang

Zhang

Liu

et al. 2010

Analog Integr Circ Sig Process

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In this paper, a clock-free decoder and a continuous backscatter link frequency (CBLF) generator for EPCglobal Gen2 UHF radio frequency identification (RFID) transponders are presented. In order to reduce power consumption, the high frequency clock used in the decoder circuit is replaced by two analog integrators and two comparators. In addition, a relaxation oscillator controlled by another integrator generates a CBLF. Measurement results show that the generated CBLF meets the Gen2 protocol at all possible conditions. The total power of the decoder and CBLF generator is 0.84 lW at 1 V operating voltage. As a result, the tag with the proposed circuit can acquire longer read range and higher read rates.

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“…Table 1 presents a current overview of the power consumption of various types of RFID-based passive nodes that also include the WPSN nodes. The RFID tag-based digital processor design reported in Man et al (2007) and Yang et al (2010) is a conventional fixed function IC, implemented as a non-programmable state machine that responds with a hard-coded ID when queried by the interrogator. In Cho et al (2005) and Yin et al (2010), the sensor integrated passive RFID tag has a fixed ID assigned to each sensor in order to support maintenance and field deployment of many sensors.…”

Section: Introductionmentioning

confidence: 99%

“…The associated digital processor does not support any arbitrary computation and typically reports sensed data in addition to the RFID tag functionality. There has been a lot of research work with regard to reducing the power consumption of such nodes (Man et al, 2007;Yang et al, 2010;Sai et al, 2012aSai et al, , 2012cSai et al, , 2010dSai et al, , 2012e, 2010. Wireless identification and sensing platform (WISP) is a battery-free sensing and computation platform that uses a low power full programmable microcontroller that enhances the functionality of the RFID tag-based sensing (Joshua et al, 2006;Alanson et al, 2007).…”

Section: Introductionmentioning

confidence: 99%

Low power 8051-MISA-based remote execution unit architecture for IoT and RFID applications

Sai

Mickle

2013

IJCAD

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Abstract:Using the existing microcontrollers in radio frequency identification (RFID)-based passive nodes requires too much power. There is a need to explore specific instruction sets of such microcontrollers based on target applications for low power. In this context, this paper describes a low-power wireless distributed single instruction multiple data (SIMD) architecture concept. This concept involves having the data and program instructions stored on a powered interrogator providing wireless supervisory control for the passive node that has a basic processing core called the remote execution unit (REU). This paper also proposes a novel REU architecture using a minimal instruction set architecture (MISA) based on 8051 µC with the goal of reducing power consumption of a wireless passive node. Post-layout simulation results indicate significant reduction in power consumption and the area occupied by REU when compared to an existing 8051 core design. This low-power programmable REU architecture targets internet of things (IoT) and passive RFID applications.

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Design and Implementation of a Low-power Baseband-system for RFID Tag

Cited by 31 publications

References 0 publications

Design Considerations for the Digital Core of a C1G2 RFID Tag

Design Considerations for the Digital Core of a C1G2 RFID Tag

A clock-free decoder and continuous BLF generator for EPCglobal Gen2 UHF RFID tags

Low power 8051-MISA-based remote execution unit architecture for IoT and RFID applications

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