Design and Implementation of a Configurable Heterogeneous Multicore SoC With Nine CPUs and Two Matrix Processors

Kondo, Hiroyuki; Nakajima, M.; Masui, N.; Otani, Sugako; Okumura, N.; Takata, Y.; Nasu, Takashi; Takata, Hiroshi; Higuchi, Takashi; Sakugawa, M.; Fujiwara, Hidenori; Ishida, Kazuya; Ishimi, K.; Kaneko, Satoshi; Itoh, Teruyuki; Sato, Mitsuhisa; Yamamoto, Osamu; Arimoto, Kazutami

doi:10.1109/jssc.2008.917528

Cited by 22 publications

(10 citation statements)

References 12 publications

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“…In this example, the pixel [0,1] is copied to two memory locations: 0x01 and 0x05. Similarly, the pixel [1,2] is copied to 0x04 and 0x08. Even though we need to access only 8 pixels, we have to transfer 10 pixels to the local memory modules where two of them are duplicated.…”

Section: Previous Partitioning Methods and Their Problems Inmentioning

confidence: 99%

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Memory-Access-Driven Context Partitioning for Window-Based Image Processing on Heterogeneous Multicore Processors

Waidyasooriya

Ohbayashi

Hariyama

et al. 2012

IEICE Trans. Inf. & Syst.

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SUMMARYAccelerator cores in low-power heterogeneous processors have on-chip local memories to enable parallel data access. The memory capacities of the local memories are very small. Therefore, the data should be transferred from the global memory to the local memories many times. These data transfers greatly increase the total processing time. Memory allocation technique to increase the data sharing is a good solution to this problem. However, when using reconfigurable cores, the data must be shared among multiple contexts. However, conventional context partitioning methods only consider how to reuse limited hardware resources in different time slots. They do not consider the data sharing. This paper proposes a context partitioning method to share both the hardware resources and the local memory data. According to the experimental results, the proposed method reduces the processing time by more than 87% compared to conventional context partitioning techniques.

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Section: Previous Partitioning Methods and Their Problems Inmentioning

confidence: 99%

“…Therefore, an effective way to implement image processing in mobile appliances is to use low-power heterogeneous multicore processors that contain different cores such as CPUs and accelerators. Examples of heterogeneous multi-core processors are [1] and [2]. The former has multiple cores of CPUs and dynamically reconfigurable ALU arrays.…”

Section: Introductionmentioning

confidence: 99%

Memory-Access-Driven Context Partitioning for Window-Based Image Processing on Heterogeneous Multicore Processors

Waidyasooriya

Ohbayashi

Hariyama

et al. 2012

IEICE Trans. Inf. & Syst.

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show abstract

“…The "micro clustering model" is a novel technique that organizes multiple CPUs into groups with multiple operating systems running on each group simultaneously [1]. This multiple operating system platform can make the appropriate allocation of roles such as a general purpose operating system and a real-time operating system among multiple operating systems.…”

Section: Multicore Hypervisormentioning

confidence: 99%

Software architecture of a secure multimedia system using a multicore SoC and software virtualization

Kondo

Yamamoto

Otani

et al. 2009

2009 Digest of Technical Papers International Conference on Consumer Electronics

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“…Each core is synthesizable and includes a FPU, a MMU, three 8KB memories for L1 Caches (I/D), and a local memory. The control processor is a symmetric multiprocessor (SMP) and supports a core grouping mode that divides cores into several groups [7]. The pipelined bus is connected to a 512KB L2 cache.…”

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confidence: 99%

Peach: A Multicore Communication System on Chip with PCI Express

et al. 2011

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Energy-aware systems, DependabilityRecent trends using computing clusters point to a growing demand for high compute density environments in various application fields such as server appliances including distributed web servers.Distributed web servers need many server nodes and low-latency/high-bandwidth network for operating a massive amount of web services including distribution of high-definition movies. In these computing clusters, power consumption and system cost have increased. Therefore, it is vital to downsize computing cluster without loss of high dependability including fault tolerance.To realize high performance, power-aware and highly dependable network, we have proposed a small computing cluster for embedded systems. This small computing cluster has low power computing nodes such as PCs and embedded CPUs. It also has a communication link between the computing nodes called PEARL (PCI Express Adaptive and Reliable Link) [1].Commodity network devices such as Gigabit Ethernet (GbE) and InfiniBand are not sufficient for small computing clusters. InfiniBand is a switched fabric communication link used in high-performance computing and enterprise data centers. It achieves high reliability but power consumption is relatively high [2]. GbE is a cost and power rival of InfiniBand. However, GbE does not match transmission performance of InfiniBand.In order to achieve both high performance and low power consumption, PEARL uses PCI Express 2/28 (PCIe) [3], which is a high-speed serial I/O interface standard in PCs, not only for connecting peripheral devices but also as a communication link between computing nodes.To implement PEARL, a communication device, PEACH (PCI Express Adaptive Communication Hub) which acts as a switching device, has been developed. PCIe transfers packets point-to-point bidirectionally with high bandwidth. However it connects only between a Root Complex (RC) and Endpoints (EPs).Therefore, a problem exists in that PCIe interfaces on PCs cannot be connected to each other, because every node CPU in the computing node is an RC. To solve this problem, each node CPU is equipped with a network interface card with PEACH. The node CPUs are connected to each other by a PCIe cable.To pair an RC with EPs at each end of the PCIe cable, PEACH can switch the RC port and EP ports to connect two computing nodes peer-to-peer.PEACH can address two computing nodes as peers, breaking the traditional PCIe limit of only linking to a single master. PEACH overviewThe communication device, PEACH, has four PCIe Rev.2.0 ports with four lanes each, and employs an eight-core control processor [4]. There are several advantages of using of PEACH in the proposed network. Four PCIe ports can broaden the scope of selection of network topology. The high bandwidth of 20Gbps/port is equal to that of InfiniBand DDR 4x. The multicore control processor performs fault handling and system monitoring / logging for dependability. The multicore processor also controls the network system for power awareness. Figure 1 shows a prototype...

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Design and Implementation of a Configurable Heterogeneous Multicore SoC With Nine CPUs and Two Matrix Processors

Cited by 22 publications

References 12 publications

Memory-Access-Driven Context Partitioning for Window-Based Image Processing on Heterogeneous Multicore Processors

Memory-Access-Driven Context Partitioning for Window-Based Image Processing on Heterogeneous Multicore Processors

Software architecture of a secure multimedia system using a multicore SoC and software virtualization

Peach: A Multicore Communication System on Chip with PCI Express

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