Design and implementation of 16 × 16 multiplier using Vedic mathematics

ROI-based Compression on Radiological Image by Urdhva-Tiryagbhyam and DWT Over FPGA

“…The work was carried out in FPGA and outcomes are found with reduced delay and memory demands compared to the traditional multiplier. Nearly similar work was also carried out by Sharma and Goyal [31] most recently only with a difference that actual work of Pohokar [30] was implemented in FPGA in 2015 and same work was also published by Sharma and Goyal [31] in H-Spice in 2016. Singh and Sasamal [32] have presented a study where binary Vedic multiplier is implemented over cadence tool using adiabatic logic.…”

“…An exactly similar version of work is also carried out by Kodali et al [29] in the same year. Usage of Vedic mathematics was found in work carried out by Pohokar et al [30]. The work was carried out in FPGA and outcomes are found with reduced delay and memory demands compared to the traditional multiplier.…”

High Speed Vedic Multiplier Based Review With Its Proposed Implementation for Parallel Fir Filter

“…Similarly multiplication can be done for any digital or binary numbers using Urdhva Triyagbhyam algorithm [5]. The block diagram for 4 bit multiplier using Urdhva Triyagbhyam algorithm is shown in Fig.…”

“…Reversible logic gates reduce the power dissipation and make the system more efficient. 16x16 Multiplier using Urdhva Tiryagbhyam algorithm is presented in [5]. Later implementation of Vedic 16x16 multiplier using binary to excess converter (BEC) is designed [6].…”

“…The partial product is then shifted after the multiplication of one bit of multiplier with multiplicand. After the multiplication process of all the multiplicand bits with all the multiplier bits, finally all the partial products are added [5] [6]. Addition is performed with normal carry propagate adder.…”