Design and implementation challenges for adoption of the IEEE 1500 standard

Higgins, Michael S.; MacNamee, Ciaran; Mullane, Brendan

doi:10.1049/iet-cdt.2008.0141

Cited by 5 publications

(4 citation statements)

References 11 publications

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“…First chip is lowermost. 1 1, 2 SI C 2 1, 2, 3 SI C 3 1, 2, 3, 4 SI C 4 1, 2, 3, 4, 5 SI C 5 1, 2, 3, 4, 5, 6 SI C 6 1, 2, 3, 4, 5, 6, 7 SI C 7 1, 2, 3, 4, 5, 6, 7, 8 SI C 8 1, 2, 3, 4, 5, 6, 7, 8, 9 SI C 9 1, 2, 3, 4, 5, 6,7,8,9,10 are kept constant for all chips in the stack for both Set 1 and Set 2, to emphasize the difference among the expected total test times. However, the yield values for Set 1 and Set 2 are changed to emphasize the differences among the test flows obtained.…”

Section: Methodsmentioning

confidence: 99%

“…Several works have addressed test planning for core-based ICs having a single chip with the aim of optimizing the test cost [2,6,7]. Design and optimization of test architecture for non-stacked ICs with IEEE 1500 is described in [4,5,11,15]. In [5], Iyengar et al address optimization of test access mechanisms (TAMs) for System-on-Chips (SoCs) to reduce core-test time by balancing core scan chains.…”

Section: Related Workmentioning

confidence: 99%

“…• Scheme 2, the TAM for the lowest chip is optimized and that TAM architecture is used for all chips in the 3D Stacked IC. In this case, all chips use the TAM 1), (0), (1) (1, 1), (0), (1) SI C 2 (1, 1, 1), (0, 0), (1) (1, 1, 1), (0, 0), (1) SI C 3 (1, 1, 1, 1), (0, 0, 0), (1) (1, 1, 1, 1), (0, 0, 0), (1) SI C 4 (1, 1, 1, 1, 1), (0, 0, 0, 0), (1) (1, 1, 1, 1, 1), (0, 0, 0, 0), (1) SI C 5 (1, 1, 1, 1, 1, 1), (0, 1, 0, 0, 0), (1) (1, 1, 1, 1, 1, 1), (0, 1, 0, 0, 0), (1) SI C 6 (0, 0, 1, 1, 1, 1, 1), (1, 0, 1, 0, 0, 0), (1) (1, 1, 1, 1, 1, 1, 1), (0, 1, 0, 0, 0, 0), (1) SI C 7 (1, 1, 1, 1, 1, 1, 1, 1), (0, 0, 0, 0, 0, 1, 0), (1) (1, 1, 1, 1, 1, 1, 1, 1), (0, 1, 0, 0, 0, 0, 0), (1) SI C 8 ( 1, 1, 1, 1, 1, 1, 1, 1, 1), (0, 1, 0, 0, 1, 0, 0, 0), (1) (1, 1, 1, 1, 1, 1, 1, 1, 1), (0, 1, 0, 0, 1, 0, 0, 0), (1) SI C 9 ( 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), (0, 1, 0, 0, 1, 0, 0, 0, 0), (1) (1, 1, 1, 1, 1, 1, 1, 1, 1, 1), (0, 1, 0, 0, 1, 0, 0, 0, 0), (1) Set 2 SI C 1 (0, 0), (0), (1) (0, 0), (0), (1) SI C 2 (0, 0, 0), (0, 0), (1) (0, 0, 0), (0, 0), (1) SI C 3 (0, 0, 1, 1), (1, 0, 0), (1) (0, 0, 1, 1), (0, 1, 0), (1) SI C 4 (0, 0, 0, 1, 1), (0, 0, 1, 0), (1) (0, 0, 0, 1, 1), (0, 0, 1, 0), (1) SI C 5 (0, 0, 0, 1, 1, 1), (0, 0, 1, 1, 0), (1) (0, 0, 0, 1, 1, 1), (0, 0, 1, 1, 0), (1) SI C 6 (0, 0, 1, 1, 1, 1, 1), (0, 0, 1, 1, 0, 0), (1) (0, 0, 0, 1, 1, 1, 1), (0, 0, 1, 1, 0, 0), (1) SI C 7 (0, 0, 0, 1, 1, 1, 1, 1), (0, 0, 1, 1, 1, 0, 0), (1) (0, 0, 0, 1, 1, 1, 1, 1), (0, 0, 1, 1, 1, 0, 0), (1) SI C 8 (0, 0, 0, 1, 1, 1, 1, 1, 1), (0, 0, 1, 1, 1, 0, 0, 0), (1) (0, 0, 0, 1, 1, 1, 1, 1, 1), (0, 0, 1, 1, 1, 0, 0, 0), (1) SI C 9 (0, 0, 0, 1, 1, 1, 1, 1, 1, 1), (0, 0, 1, 1, 1, 0, 0, 0, 0), (1) (0, 0, 0, 1, 1, 1, 1, 1, 1, 1), (0, 0, 1, 1, 1, 0, 0, 0, 0), (1) [12] is extended from only accepting WSPT to allow an arbitrary test flow.…”

Section: Test Architecture Designmentioning

confidence: 99%

See 2 more Smart Citations

Test Flow Selection for Stacked Integrated Circuits

et al. 2019

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Integrated circuits (ICs) with a single chip (die) are typically tested with a test flow consisting of two test instances: (1) wafer sort for the bare chip and (2) package test for the packaged IC. For ICs with stacked chips -3D Stacked ICs -there are many possible test instances, even more test flows, and no commonly used test flow. In this paper, we propose a test flow selection algorithm (TFSA) to obtain a test flow for a given 3D Stacked IC. The TFSA results in a test flow for a given 3D Stacked IC, such that the expected total test time to produce each good package is minimized. We implemented the TFSA, three straightforward test flow schemes and an exhaustive search, and experimentally compared the test flow schemes on three different test architecture design approaches. The results demonstrate the importance to have methods both to select the test flow and design the test architecture.Publisher's Note Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations. Breeta SenGupta received her M.Sc. degree from Indian Institute of Technology, Kharagpur, India, in 2009. She pursues her Ph.D. at the Department of Electrical and Information Technology, Lund University, Sweden. Her area of research includes 3D integration and testing. Breeta is currently engaged in development and verification of RF ASIC at Ericsson, Sweden.

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Section: Methodsmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Test Architecture Designmentioning

confidence: 99%

See 1 more Smart Citation

Test Flow Selection for Stacked Integrated Circuits

et al. 2019

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“…The standard defines core wrapper architecture, which is analogous to the use of IEEE 1149.1 for boundary scan testing of ICs. Higgins et al [28] use this wrapper architecture to simultaneously test multiple cores; their paper outlines the use of on‐chip test controllers and reuse of the on‐chip bus for test purposes. Prior work of others such as Lee et al [29], Huang et al [30] and Krstic et al [31], also highlight the benefits of using on‐chip resources to implement test.…”

Section: Standard Interfacesmentioning

confidence: 99%

On‐chip support for software verification and debug in multi‐core embedded systems

2013

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The challenges in silicon testing and debug of complex integrated circuits are well understood. Where these circuits include multiple processor cores there is also a dramatic increase in the complexity of verifying and debugging the associated software; with much of this complexity being because of the inherent lack of visibility over internal signals which integration brings. The trend to-date has been to rely upon silicon test interfaces to provide access to internal signals required for software verification and debug. However, it is questionable whether this is sufficient for real-time systems or future designs with increasing processor cores. This study examines the on-chip technology supporting software verification and debug in current designs and proposes enhancements in this area. As much of this technology is primarily intended for silicon test it is lacking in terms of I/O bandwidth, which is a significant limitation for software verification and debug. The authors propose their alternative approach of using an on-chip coprocessor and debug circuitry to address this principal limitation; and describe an embedded application where this approach was successfully applied to monitor timing requirements and detect failures. The authors also outline how this approach could be applied as an architectural solution for formal runtime verification.

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Wrapper scan chains balance algorithm base on twice assigned by difference and mean value

Deng

Qiao

2015

2015 Ieee Autotestcon

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Design and implementation challenges for adoption of the IEEE 1500 standard

Cited by 5 publications

References 11 publications

Test Flow Selection for Stacked Integrated Circuits

Test Flow Selection for Stacked Integrated Circuits

On‐chip support for software verification and debug in multi‐core embedded systems

Wrapper scan chains balance algorithm base on twice assigned by difference and mean value

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