Design and FPGA implementation of Min-Sum algorithm and its variants

Tolouei, Sina

doi:10.22215/etd/2008-07687

Cited by 1 publication

(2 citation statements)

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“…For reference, BER curves of standard floating-point BP and MS are given in the figure as well. We have also simulated the three algorithms and the performance curves obtained from simulations match very well with the test results from the FPGA implementation [7]. (1) prev_input (2) prev_input (3) 6 adder_input (1) adder_input (2) adder_input (4) adder_input ( As can be seen in Fig.…”

Section: Fig 4-variable Node Architecture For Sr-ms-llrmentioning

confidence: 55%

“…In high-speed applications, parallel implementations of iterative message-passing algorithms for the decoding of LDPC codes are of great interest [4]- [6]. To reduce the complexity of the algorithm, which translates to reducing the area and power consumption as well as increasing the throughput, researchers have used min-sum (MS) algorithm and its modifications as prime candidates for implementing iterative decoders [5], [6], [7]. In [5], a bit-serial approximation of MS for a fully-parallel LDPC decoder is implemented in FPGA.…”

Section: Introductionmentioning

confidence: 99%

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FPGA implementation of variants of min-sum algorithm

Tolouei

Banihashemi

2008

2008 24th Biennial Symposium on Communications

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This paper presents the FPGA implementation of a number of popular decoding algorithms for a regular rate-1/2 low density parity check code with block length 504 bits. The so-called minsum (MS) algorithm and two of its variants, known as MS with successive relaxation (SR-MS) and MS with unconditional correction (MS-UC), are implemented. We implement the algorithms on a Xilinx XC2VP100 FPGA device with 4-bit quantization. We show that for MS-UC, the circuit utilization increases by about 2% compared to standard MS and that the throughput is the same as that of MS. For SR-MS, the device utilization is increased by about 26% and the throughput is decreased by approximately 20% compared to standard MS. While the throughput and the area and power consumption of our implementation is comparable to the most recent FPGA implementations of LDPC decoders, ours is the first attempt at implementing an iterative decoding algorithm with memory (SR-MS).

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Section: Fig 4-variable Node Architecture For Sr-ms-llrmentioning

confidence: 55%