Design and FPGA Implementation of Compensator for Sharpening CIC Filter

Abstract

This paper presents a novel compensator design for sharpened CIC (cascade-integrator-comb) proposed in the literature. Sharpened CIC provides higher aliasing attenuation than the CIC filter. However, its passband droop is higher than the corresponding CIC filter and must be compensated. Our motivation was to design a decimator with better compensation than the one proposed in the literature. The proposed decimation filter has two coefficients and six adders. The coefficients are determined using particle swarm optimization (PSO) in MATLAB. Two designs are presented. The first one has two multipliers and six adders. The second is a multiplierless design obtained by presenting optimal coefficients in the signed power-of-two (SPT) form. The proposed design is compared with the design from the literature. The designed compensator is implemented in a field-programmable gate array (FPGA). Details of the implementation are described in the paper.