Design and FPGA-based multi-channel, low phase-jitter ADPLL for audio data converter

Ameur, Noura Ben; Nouri, Mohammad; Loulou, Mourad

doi:10.1109/newcas.2013.6573588

Cited by 2 publications

(2 citation statements)

References 9 publications

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“…Then, the practical applicability of the polyphase-clocked architecture is then limited to small number of phases. It is noted that sophisticated techniques can indeed be used to interleave many ADC operations leading to high throughput albeit at the cost of using on-chip calibration techniques to address challenges with clock synchrony and phase jitter [55,56]. The proposed system uses a single-phase clock.…”

Section: Digital Enginementioning

confidence: 99%

Wide‐band aperture array using a four‐channel manifold‐type planar multiplexer and digital 2‐D IIR filterbank

Sengupta

Madanayake

Gómez‐García

et al. 2016

Circuit Theory & Apps

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SUMMARYEmerging wide-band communications and spectrum-sensing systems demand support for multiple electronically scanned beams while maintaining a frequency independent, constant far-field beam width. Realizing existing phased-array technology on a digital scale is computationally intensive. Moreover, digitizing wide-band signals at Nyquist rate requires complex high-speed analog-to-digital converters (ADCs), which is challenging for real developments driven by the current ADC technology. A low-complexity alternative proposed in this paper is the use of radio-frequency (RF) channelizers for spectrum division followed by sub-sampling of the RF sub-bands, which results in extensive reduction of the necessary ADC operative frequency. The RF-channelized array signals are directionally filtered using 2-D digital filterbanks. This mixed-domain RF/digital aperture array allows sub-sampling, without utilizing multi-rate 2-D systolic arrays, which are difficult to realize in practice. Simulated examples showing 14-19 dB of rejection of wide-band interference and noise for a processed bandwidth of 1.6 GHz are demonstrated. The sampling rate is 400 MHz. The proposed VLSI hardware uses a single-phase clock signal of 400 MHz. Prototype hardware realizations and measurement using 65-nm Xilinx field-programmable gate arrays, as well as Cadence RTL synthesis results including gate counts, area-time complexity, and dynamic power consumption for a 45-nm CMOS circuit operating at B DC = 1.1 V, are presented.

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Section: Digital Enginementioning

confidence: 99%

Wide‐band aperture array using a four‐channel manifold‐type planar multiplexer and digital 2‐D IIR filterbank

Sengupta

Madanayake

Gómez‐García

et al. 2016

Circuit Theory & Apps

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“…FPGAs could be explored [73]. .j1(inj1),.j2(inj2),.j3(inj3),.j4(inj4),.j5(inj5),.j6(inj6),.j7(inj7),.j8(inj8),.j9(inj9),.j1 0(inj10), .j11(inj11),.j12(inj12),.j13(inj13),.j14(inj14),.j15(inj15),.j16(inj16),.j17(inj17),.j1 8(inj18),.j19(inj19),.j20(inj20), .j21(inj21),.j22(inj22),.j23(inj23),.j24(inj24),.j25(inj25),.j26(inj26),.j27(inj27),.…”

Section: Future Workmentioning

confidence: 99%

A Fully Synthesized Injection Locked Ring Oscillator Based on a Pulse Injection Locking Technique

Li¹

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This thesis proposes a novel, all synthesized, Injection Locked Ring Oscillator (ILRO). It employs a digitally tunable oscillator and a pulse injection locking technique. The frequency tuning range of the free running oscillator is from 210 MHz to 1.8 GHz with a 1.1 volt power supply. The tuning range from 1.0 to 1.8 GHz can be achieved with 215 tuning steps with a maximum step size of 11.2 MHz, that is well within the worst case 75MHz (3rd sub-harmonic) and 32 MHz (9 th sub-harmonic) locking range of the oscillator.The design occupies 127.5 um by 31.5 um of chip area and is implemented in TSMC's 65nm CMOS technology. For 3rd harmonic injection locking, the ILRO's RMS jitter is 192.7 fs (1 KHz to 40 MHz) with a phase noise of -130.9 dBc/Hz at 1 MHz offset from the 1.62GHz carrier while consuming 7.15 mW of power.iii

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Design and FPGA-based multi-channel, low phase-jitter ADPLL for audio data converter

Cited by 2 publications

References 9 publications

Wide‐band aperture array using a four‐channel manifold‐type planar multiplexer and digital 2‐D IIR filterbank

Wide‐band aperture array using a four‐channel manifold‐type planar multiplexer and digital 2‐D IIR filterbank

A Fully Synthesized Injection Locked Ring Oscillator Based on a Pulse Injection Locking Technique

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