Design and Fabrication of Vertically-Integrated CMOS Image Sensors

Abstract

Technologies to fabricate integrated circuits (IC) with 3D structures are an emerging trend in IC design. They are based on vertical stacking of active components to form heterogeneous microsystems. Electronic image sensors will benefit from these technologies because they allow increased pixel-level data processing and device optimization. This paper covers general principles in the design of vertically-integrated (VI) CMOS image sensors that are fabricated by flip-chip bonding. These sensors are composed of a CMOS die and a photodetector die. As a specific example, the paper presents a VI-CMOS image sensor that was designed at the University of Alberta, and fabricated with the help of CMC Microsystems and Micralyne Inc. To realize prototypes, CMOS dies with logarithmic active pixels were prepared in a commercial process, and photodetector dies with metal-semiconductor-metal devices were prepared in a custom process using hydrogenated amorphous silicon. The paper also describes a digital camera that was developed to test the prototype. In this camera, scenes captured by the image sensor are read using an FPGA board, and sent in real time to a PC over USB for data processing and display. Experimental results show that the VI-CMOS prototype has a higher dynamic range and a lower dark limit than conventional electronic image sensors.

Simultaneous Control of Carriers and Localized Spins with Light in Organic Materials

“…Photoconduction and its related phenomena have been known for quite some time, and have attracted a significant amount of scientific attention 1. Photoconduction is applied in devices, sensors, detectors, and energy converters, such as charge‐coupled devices, complementary metal oxide‐semiconductor image sensors, and photovoltaic cells, in addition to other advanced applications under investigation 2, 3. In all known photoconductors, photoexcitation (PE) controls only the carriers.…”

Digital Pixel Sensor Array with Logarithmic Delta-Sigma Architecture

“…Skorka and Joseph [17] argue that vertical integration offers a path, compatible with the proposed architecture, to lower DL. They demonstrate a logarithmic VI-CMOS APS array, added to Figure 8 (design 26), that exhibits low DL and wide DR. SR was limited by lack of access to fine-pitch vertical integration, such as through-silicon vias.…”

“…Skorka et al review designs 1–24. Designs 25 and 26 are from the University of Alberta, where the former is this work and the latter is by Skorka and Joseph [17]. …”

“…State-of-the-art image sensors also suffer from high DL, relative to the human eye, but their SR is competitive [4,16]. Fortunately, emerging methods for vertical integration are compatible with the proposed architecture, and these methods are expected to enable lower DL and higher SR [17]. …”

Bio-inspired design: nonlinear digital pixels for multiple-tier processes

“…Skorka and Joseph 46 have presented a VI-CMOS APS array that was prepared by flip-chip bonding, a traditional process for multiple-tier stacking. The prototype is composed of a 0.8 µm Teledyne-DALSA die and a photodetector die, where photodetectors are based on a-Si:H. A photo of the prototype is shown in Fig.…”