Abstract:This study aims to develop a novel CMOS-MEMS logic gate via commercially available CMOS process (TSMC, 2P4M ). Compared to existing CMOS MEMS designs, which uses foundry processes, the proposed design imposes several new challenges including: carrying two voltage levels on a non-warping suspended plate, metalto-metal contact, and etc. Different combinations of oxide-metal films and post-CMOS process are investigated to achieve a non-warping suspended structure layer. And different wet etchants are investigated… Show more
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