Design and Direct Assembly of 2.5D/3D Rigid Silicon Interposer on PCB

Abstract

Silicon interposer is emerging as a vehicle for integrating dies with sub 50um bump pitch in 2.5D/3D configuration. Benefits of 2.5D/3D integration are well explained in the literature, however, cost and reliability is a major concern especially with the increase in interposer size. Among the challenges, reliability issues such as warpage, cracks and thermal-stresses must be managed, in addition, multi-layer build-up flip chip substrate cost and its impact on the overall yield must be considered. Because of these challenges, 2.5D/3D silicon interposer has developed a reputation as a costly process. To overcome the reliability challenges and cost associated with typical thin interposer manufacturing and assembly, a rigid silicon interposer type structure is disclosed. In this study, interposer with thickness of greater than 300um is referred to as rigid interposer. Rigid silicon interposer is directly assembled on PCB without the need for intermediary substrate. This eliminates the need for an intermediary substrate, thin wafer handling, wafer bonding/debonding procedures and Through Silicon Via (TSV) reveal processes, thus, substantially reducing the cost of 2.5D/3D integrated products while improving reliability. A 10X10mm2 rigid silicon interposer test vehicle with 310um thickness was designed and fabricated. BGA side of the interposer with 1mm ball pitch was bumped with eutectic solder balls through a reflow process. Interposer was then assembled on a 50X50mm2 FR-4 PCB. We present design and direct assembly of the rigid silicon interposer on PCB followed by temperature cycle results using CSAM images at 250, 500, 750 and 1000 cycles. It is shown that all samples successfully passed the temperature cycle stress test.

Inkjet printing technology for increasing the I/O density of 3D TSV interposers

“…Electrical testing before and after temperature cycling experiments showed that temperature cycles of up to 1000 cycles did not cause any open circuits or significantly affect the electrical resistance of the via chains with printed dielectric polymer filling, confirming the findings in Ref. 10. Thus, the difference of the CTEs of Si, Cu, and the dielectric polymer do not appear to affect the electrical functionality of the TSVs.…”

“…It was also demonstrated that solder balls can be printed successfully on the interposers, thereby demonstrating the potential for a four-times increased I/O density compared to the same TSV platform used in Ref. 10 but without filling of the hollow vias with the dielectric polymer. …”

“…The proposed approach, compared to the technology used in Ref. 10, enables four times higher I/O densities without using the nextgeneration TSV node. This has significant advantages because moving to the next-generation TSV node would involve smaller TSV dimensions with significantly increased fabrication challenges.…”

“…Figure 9b illustrates the dramatic increase in I/O density enabled by our approach, without the need for using next-generation TSV with reduced diameters. The conventional approach 10 …”

“…Temperature cycling reliability testing was performed after the dielectric filling of the metal TSVs to benchmark against the initial reliability tests performed on the standard hollow metal TSVs 10 . The TSVs used for our experiments are identical (taken from the same wafer batch) to the TSVs used in Ref.…”