Design and development of a real time scheduling algorithm for mixed task set on multi-core processors

Digalwar, Mayuri; Gahukar, Pravin; Mohan, Sudeept

doi:10.1109/ic3.2014.6897184

Cited by 6 publications

(2 citation statements)

References 21 publications

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“…It calls for the hardware support for scheduler. Digalwar et al [33] present a real time scheduling algorithm for mixed task set on homogeneous multi-core platform. But the heterogeneous cores are not considered.…”

Section: Introductionmentioning

confidence: 99%

A task-efficient sink node based on embedded multi-core SoC for Internet of Things

Qiu

Zhao

et al. 2018

Future Generation Computer Systems

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h i g h l i g h t s • TESN processes tasks in parallel. It has heterogeneous architecture, including one master core and seven slave cores. • TESN adopts WLC to allocate tasks, which balances the load of each slave core and improves the tasks processing speed obviously. • Compared with single core system, TESN effectively reduces the congestion situation. • The performance of WLC based on multi-core processor is better than RR when the number of soft cores is more than two.

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Section: Introductionmentioning

confidence: 99%

A task-efficient sink node based on embedded multi-core SoC for Internet of Things

Qiu

Zhao

et al. 2018

Future Generation Computer Systems

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“…On the other hand, CoWare uses a set of un-timed reactive System C tasks communicating through a Transaction Level Model interface. In work of [7] they used an extended Task Graph (eTG) as design entry, and generated a scheduled System C performance model that is further synthesized into interacting H/W modules with control unit implemented as FSMs [8,9,10].…”

Section: Introductionmentioning

confidence: 99%

Designing an Architecture Level Model for Multi-Core Systems

Youness

2014

JES. Journal of Engineering Sciences

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The Architecture Level Model (ALM) as a design in space exploration in the early phases of the design process can have a dramatic impact on the area, speed, and power consumption of the resulting systems. A multi-core system is an integrated circuit containing multiple processor cores that implements most of the functionality of a complex electronic system and some other components like FPGA/ASIC on a single chip. In this paper, we present a new approach to synthesize multi-core system architectures from Task Precedence Graphs (TPG) models. The front end engine applies efficient algorithm for scheduling and communication contention resolving to obtain the optimal multi-core system architecture in terms of number of processor cores, number of busses, task-to-processor/channel-to-bus mapping, optimal schedule, and Hardware/Software partition. The back end engine generates a System C simulation model using a well-known commercial tool model generation library to form the architecture level model. The viability and potential of the approach is demonstrated by a case study.

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Q-Learning Based Optimisation Framework for Real-Time Mixed-Task Scheduling

Meng

Huang

et al. 2021

Cyber-Physical Systems

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Design and development of a real time scheduling algorithm for mixed task set on multi-core processors

Cited by 6 publications

References 21 publications

A task-efficient sink node based on embedded multi-core SoC for Internet of Things

A task-efficient sink node based on embedded multi-core SoC for Internet of Things

Designing an Architecture Level Model for Multi-Core Systems

Q-Learning Based Optimisation Framework for Real-Time Mixed-Task Scheduling

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