Design and Characterization of Bulk Driven MOS Varactor based VCO at Near Threshold Regime

Dani, Lalit Mohan; Mishra, Neeraj; Banchhor, Shashank; Miryala, Sandeep; Doneria, Aditya; Bulusu, Anand

doi:10.1109/s3s.2018.8640143

Cited by 4 publications

(2 citation statements)

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“…It is worth noticing here that the investigation of the Process-Voltage-Temperature corners, the Montecarlo analysis, and the Post-Layout-Simulations are necessary steps for the robust design of oscillators [55][56][57] and Frequency Dividers [58,59]. Nevertheless, in the absence of cryogenic DKs, these investigations can be carried out only at room temperature.…”

Section: Design Guidelinesmentioning

confidence: 99%

On the VCO/Frequency Divider Interface in Cryogenic CMOS PLL for Quantum Computing Applications

2021

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The availability of quantum microprocessors is mandatory, to efficiently run those quantum algorithms promising a radical leap forward in computation capability. Silicon-based nanostructured qubits appear today as a very interesting approach, because of their higher information density, longer coherence times, fast operation gates, and compatibility with the actual CMOS technology. In particular, thanks to their phase noise properties, the actual CMOS RFIC Phase-Locked Loops (PLL) and Phase-Locked Oscillators (PLO) are interesting circuits to synthesize control signals for spintronic qubits. In a quantum microprocessor, these circuits should operate close to the qubits, that is, at cryogenic temperatures. The lack of commercial cryogenic Design Kits (DK) may make the interface between the Voltage Controlled Oscillator (VCO) and the Frequency Divider (FD) a serious issue. Nevertheless, currently this issue has not been systematically addressed in the literature. The aim of the present paper is to investigate the VCO/FD interface when the temperature drops from room to cryogenic. To this purpose, physical models of electronics passive/active devices and equivalent circuits of VCO and the FD were developed at room and cryogenic temperatures. The modeling activity has led to design guidelines for the VCO/FD interface, useful in the absence of cryogenic DKs.

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Section: Design Guidelinesmentioning

confidence: 99%

On the VCO/Frequency Divider Interface in Cryogenic CMOS PLL for Quantum Computing Applications

2021

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“…VCOs are one of the main building blocks of the communication systems, such as phase‐locked loops and clock and data recovery circuits [7–9]. Wider tuning range [10–15] and lower area consumption [10, 11, 16, 17] are the major advantages of the ROs over the LC oscillators. Other advantages of ROs are (i) the simplicity and ease of implementation [18–20], (ii) integrated nature [21–23], (iii) compatibility with complementary metal‐oxide semiconductor (CMOS) technology scaling [24] and (iv) the ability of oscillating at very high frequencies [11].…”

Section: Introductionmentioning

confidence: 99%