Design and Characterization of a 10 Gb/s Clock and Data Recovery Circuit Implemented with Phase-Locked Loop

Song, Jang Ho; Yoo, Tae Whan; Ko, Jeong Hoon; Park, Chang Soo Park; Kim, Jae Keun Kim

doi:10.4218/etrij.99.0199.0301

Cited by 7 publications

(5 citation statements)

References 8 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Also, two types of CDR structures are typically utilized for recovering the clock and data: open-loop type [2] and phase-locked loop type [3]- [5]. The practical design and implementation of the CDR module for the 40 Gb/s optical communication system, however, is still on the progress and actively investigated worldwide.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Performance Improvement of a 40 Gb/s PLL Clock Recovery Module Using New Frequency Acquisition and Clock Hold Circuits

Park

Woo

Kim³

et al. 2006

2006 IEEE MTT-S International Microwave Symposium Digest

View full text Add to dashboard Cite

Significant performance improvements have been obtained with a 40 Gb/s phase-locked clock recovery (CR) module for fiber optic receivers by employing a new frequency acquisition circuit in the phase-locked loop (PLL) and a clock hold circuit. The new simple frequency acquisition circuit helps to extend the frequency lock-range, obtain faster frequency acquisition, and reduce the current consumption as compared with the conventional ones. In addition, a clock hold circuit helps to prevent the loss of the clock signal in the cases of temporary input signal loss. The measured RMS jitter of the improved PLL CR module at 40 Gb/s is about 250 fs, which is significantly better than the open-loop type CR module.

show abstract

Section: Introductionmentioning

confidence: 99%

“…The CDR can be categorized by the fabrication methods: monolithic circuit implementation [1] and hybrid MIC module [2]- [5]. Also, two types of CDR structures are typically utilized for recovering the clock and data: open-loop type [2] and phase-locked loop type [3]- [5].…”

Section: Introductionmentioning

confidence: 99%

Performance Improvement of a 40 Gb/s PLL Clock Recovery Module Using New Frequency Acquisition and Clock Hold Circuits

Park

Woo

Kim³

et al. 2006

2006 IEEE MTT-S International Microwave Symposium Digest

View full text Add to dashboard Cite

show abstract

“…Two types of CDR structures are typically used for recovering the clock and data: openloop type [2,3] and phase-locked loop (PLL) type [4 -6]. A significant number of studies has been done for the design of CDR modules for 10-to 20-Gb/s data rates [1,2,5,6], and some present research on CDR for data rates greater than 40 Gb/s [4]. However, practical design and implementation of CDR modules for the 40-Gb/s optical system are still in progress and being actively investigated worldwide.…”

Section: Introductionmentioning

confidence: 99%

“…In such a case, quasi-static field solvers are used to obtain the values of these circuit elements [1,2]. Full-wave solvers that utilize techniques such as the moment method [3] or finite-difference timedomain (FDTD) [4,5] or finite-element [6] can also be used to obtain these values. In addition to providing circuit models, such techniques can also provide the scattering parameters, which provide a complete characterization of the via behavior in the frequency domain.…”

Section: Introductionmentioning

confidence: 99%

Implementation of a low‐cost phase‐locked loop clock‐recovery module for 40‐Gb/s optical receivers

Woo

Kim

Lim

et al. 2005

Micro & Optical Tech Letters

View full text Add to dashboard Cite

A low‐cost, compact, high‐performance clock‐recovery (CR) module using a new phase‐locked loop (PLL) for 40‐Gb/s optical receivers is successfully designed and implemented. The newly implemented frequency detector in the PLL helps to reduce the current consumption and also extended the frequency‐capture range. The implemented PLL clock‐recovery module demonstrates advantages over the conventional open‐loop type clock‐recovery module with a DR filter by significantly improving clock jitter, thus reducing overall module cost, and allowing the possibility of providing a proper clock signal in the case of temporary loss of NRZ input signals. The CR module exhibits error‐free operation during a 30‐min BER test with a time‐division‐multiplexing (TDM) 40‐Gb/s transmission system. © 2005 Wiley Periodicals, Inc. Microwave Opt Technol Lett 48: 312–315, 2006; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.21335

show abstract

“…The CDR module can be implemented either in the form of a monolithic circuit [1] or a hybrid microwave integrated circuit module [2]- [5]. In addition, the CDR module can be categorized according to the method of recovering the clock as either open-loop type [2] or phase-locked loop (PLL) type [3]- [6].…”

Section: Introductionmentioning

confidence: 99%

A 40 Gb/s Clock and Data Recovery Module with Improved Phase-Locked Loop Circuits

Park¹,

Kim²,

Lim³

et al. 2008

ETRI Journal

View full text Add to dashboard Cite

A 40 Gb/s clock and data recovery (CDR) module for a fiber-optic receiver with improved phase-locked loop (PLL) circuits has been successfully implemented. The PLL of the CDR module employs an improved D-type flip-flop frequency acquisition circuit, which helps to stabilize the CDR performance, to obtain faster frequency acquisition, and to reduce the time of recovering the lock state in the event of losing the lock state. The measured RMS jitter of the clock signal recovered from 40 Gb/s pseudo-random binary sequence (2 31 -1) data by the improved PLL clock recovery module is 210 fs. The CDR module also integrates a 40 Gb/s D-FF decision circuit, demonstrating that it can produce clean retimed data using the recovered clock.

show abstract

Design and Characterization of a 10 Gb/s Clock and Data Recovery Circuit Implemented with Phase-Locked Loop

Cited by 7 publications

References 8 publications

Performance Improvement of a 40 Gb/s PLL Clock Recovery Module Using New Frequency Acquisition and Clock Hold Circuits

Performance Improvement of a 40 Gb/s PLL Clock Recovery Module Using New Frequency Acquisition and Clock Hold Circuits

Implementation of a low‐cost phase‐locked loop clock‐recovery module for 40‐Gb/s optical receivers

A 40 Gb/s Clock and Data Recovery Module with Improved Phase-Locked Loop Circuits

Contact Info

Product

Resources

About