Design and Application of Faithfully Rounded and Truncated Multipliers With Combined Deletion, Reduction, Truncation, and Rounding

Ko, Hou-Jen; Hsiao, Shen-Fu

doi:10.1109/tcsii.2011.2148970

Cited by 55 publications

(21 citation statements)

References 14 publications

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“…In this section the proposed multipliers are compared with ten other multipliers: truncated1 [7], truncated2 [8], truncated3 [9], LOA [5], Momeni [15], Ma [16], Liu [13,14], Kulkani [11], Accurate3:2 (the Dadda multiplier constructed by 3:2 precise compressors), and Accurate4:2 (the Dadda multiplier constructed by 4:2 precise compressors). Table 4 shows the MSE, the delay, the number of transistors, and the product of delay and the number of transistors (PDT) of each multiplier.…”

Section: Simulationsmentioning

confidence: 99%

See 1 more Smart Citation

High Performance 8-bit Approximate Multiplier using Novel 4:2 Approximate Compressors for Fast Image Processing

Ranjbar¹,

Forghani

Bahrepour³

2018

IJIE

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Section: Simulationsmentioning

confidence: 99%

“…In other words, the compensated value is not constant any longer. Another truncated multiplier was proposed in [9] where the maximum absolute error is guaranteed to be no more than 1 unit of least position. This multiplier was implemented in Field Programmable Gate Array (FPGA), and then it was applied for image blending [10].…”

Section: Introductionmentioning

confidence: 99%

High Performance 8-bit Approximate Multiplier using Novel 4:2 Approximate Compressors for Fast Image Processing

Ranjbar¹,

Forghani

Bahrepour³

2018

IJIE

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“…For generation of compensation bias, we retain some of the partial product bits in the LS designated as LS retain . Our algorithm incorporates a new step "non-generation" and combines it with certain steps of Ko and Hsiao [17] algorithm. In "non-generation", we do not generate an initial/first product (PP 0 ), since the bits in PP 0 does not contribute significantly for the bits in final product.…”

Section: Proposed Truncated Mbe Multipliermentioning

confidence: 99%

“…Also the use of booth algorithm for partial product generation reduces the number of partial product rows by half using two's complement conversion. As two's complement conversion involves sign bits in the partial product rows, the position of placing compensation bit for "non-generation" will be different to Ko and Hsiao [17] compensation. The implementation of the algorithm for n = 8 is shown in Fig.…”

Section: Proposed Truncated Mbe Multipliermentioning

confidence: 99%

VLSI Implementation of Area-Efficient Truncated Modified Booth Multiplier for Signal Processing Applications

Vijeyakumar¹,

Sumathy²,

Elango³

2014

Arab J Sci Eng

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In this paper, hardware efficient truncated multiplier using modified booth algorithm is proposed for signed bit multiplication, such that the average absolute error is kept minimum. The proposed methodology truncates the least significant bits (LSBs) of the final product and thus minimizes the number of full adders and half adders used in partial product accumulation. This we achieve by non-generation of an initial partial product and deletion of certain LSBs in higher order partial products. To minimize the error due to non generation and omission, we add compensation bits at appropriate retained bit positions. Experimental analysis of the proposed truncation algorithm implemented in modified booth encoded multiplier using Synopsys design compiler demonstrates area saving of nearly 25.1 % for an 8×8 design. The functionality of the proposed design is verified by implementing in a signal processing system.

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“…To maintain the full accuracy of the system, a DSP architecture requires an ever-growing bit width that would be impossible or impractical to implement. One commonly used method is truncating and rounding the results with the n most significant bits so that they fit the limits of the architectural bit width [1]. The circuit area and dynamic power dissipation can also be reduced proportionally.…”

Section: Introductionmentioning

confidence: 99%

Reduced-error constant correction truncated multiplier

Wang

Cao

Xiao

2014

IEICE Electron. Express

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Constant correction truncated multiplier can minimize hardware cost and power dissipation by computing only the most significant bits of partial products. However, traditional schemes introduce large truncation errors that degenerate the accuracy of the target application. In this brief, we propose an improved scheme that can significantly reduce such truncation errors. The proposed scheme estimates an accurate compensating constant by correctly counting the probability of occurrence of the input operand and the product bits with a group of probability propagation formulas. The proposed truncated multiplier is coded in Verilog RTL, implemented in 65 nm standard cell technology, and applied in image compression and color space conversion applications. Experimental results show that our scheme achieves an average peak signal-to-noise ratio (PSNR) improvement of 4.09 dB and 2.31 dB over state-of-the-art truncation scheme in the two applications, respectively. When the same truncation error range is desired, the proposed scheme can save around 5.8% of circuit area.

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Design and Application of Faithfully Rounded and Truncated Multipliers With Combined Deletion, Reduction, Truncation, and Rounding

Cited by 55 publications

References 14 publications

High Performance 8-bit Approximate Multiplier using Novel 4:2 Approximate Compressors for Fast Image Processing

High Performance 8-bit Approximate Multiplier using Novel 4:2 Approximate Compressors for Fast Image Processing

VLSI Implementation of Area-Efficient Truncated Modified Booth Multiplier for Signal Processing Applications

Reduced-error constant correction truncated multiplier

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