Design and application of a metal wet-etching post-process for the improvement of CMOS-MEMS capacitive sensors

Abstract

This study presents a process design methodology to improve the performance of a CMOS-MEMS gap-closing capacitive sensor. In addition to the standard CMOS process, the metal wet-etching approach is employed as the post-CMOS process to realize the present design. The dielectric layers of the CMOS process are exploited to form the main micro mechanical structures of the sensor. The metal layers of the CMOS process are used as the sensing electrodes and sacrificial layers. The advantages of the sensor design are as follows:(1) the parasitic capacitance is significantly reduced by the dielectric structure, (2) in-plane and out-of-plane sensing gaps can be reduced to increase the sensitivity, and (3) plate-type instead of comb-type out-of-plane sensing electrodes are available to increase the sensing electrode area. To demonstrate the feasibility of the present design, a three-axis capacitive CMOS-MEMS accelerometers chip is implemented and characterized. Measurements show that the sensitivities of accelerometers reach 11.5 mV G −1 (in the X-, Y-axes) and 7.8 mV G −1 (in the Z-axis), respectively, which are nearly one order larger than existing designs. Moreover, the detection of 10 mG excitation using the three-axis accelerometer is demonstrated for both in-plane and out-of-plane directions.

Development of multi-axes CMOS-MEMS resonant magnetic sensor using Lorentz and electromagnetic forces

“…Fig.3a shows the chip prepared by standard TSMC 0.35µm 2P4M CMOS process. In Fig.3b, H 2 SO 4 /H 2 O 2 solution was used to remove metal and tungsten-via layers [1]. The sub-micron in-plane sensing gap was defined by the minimum line width of metal and tungsten vias for CMOS process.…”

Improvement of the microcapacitive humidity sensor by the package optimisation

“…Some researchers explicitly analysed the role of porous silicon in the reduction of parasitic capacitance for humidity sensing [8]. Some other researchers focused on the high-sensitivity capacitive humidity sensor, in which the parasitic capacitances were decreased by special electrodes design and a SiO 2 layer introduction [9]. Furthermore, dielectric structure optimisation could also be used to reduce the parasitic capacitance for a CMOS-MEMS accelerometers chip, which resulted in the sensitivities being almost one order larger than the existing design [10].…”

Design and implementation of an extremely large proof-mass CMOS-MEMS capacitive tilt sensor for sensitivity and resolution improvement

“…However, the proof-mass is limited to standard CMOS process, and further influence the sensitivity and resolution of tilt sensor. Various researches for sensitivity enhancement of the CMOS MEMS capacitive sensor have been reported [4][5][6]. For instance, the sensitivity is increased by increasing the number of sensing electrodes [4], and by reducing the size of sensing gap [5].…”

“…Various researches for sensitivity enhancement of the CMOS MEMS capacitive sensor have been reported [4][5][6]. For instance, the sensitivity is increased by increasing the number of sensing electrodes [4], and by reducing the size of sensing gap [5]. However, the approach in [4] will reduce the proof-mass.…”