Design and application of a 2500-gate bipolar macrocell array

Suzuki, Masao; Konaka, Shinsuke; Ichino, H.; Sakai, T.; Horiguchi, S.

doi:10.1109/jssc.1985.1052431

Cited by 8 publications

(1 citation statement)

References 13 publications

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“…It is known that the use of the former two approaches results in a reduction in the computation time, however, at the expense of increased interconnection and routing complexities calling for specialized layout strategies [U-141. However, CSA based array multipliers are receiving increasing attention as they offer important advantages: modularity, expandability, a high-degree of testability, and repetitive layout resulting in compact and error free designs [7][8][9][10][11][12][13][14]. In fact, they are implemented in practice with word-lengths as large as 64-bits [12].…”

Section: Introductionmentioning

confidence: 99%

A novel VLSI BiCMOS/bipolar concurrent multiplier-accumulator for DSP applications

Poornaiah¹,

Mohan²,

Ahmad

1993

Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting BIPOL-93

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In this paper, we present the design of a novel BiCMOS/Bipolar concurrent multiplier-accumulator (BICMAC) architecture that can be configured on-the-fly for selecting multiply alone or multiplyaccumulation (add/subtract) computations involving unsigned/signed 2's compliment/mixed-mode data formats for normal as well as extended precision arithmetic. The proposed BICMAC does not require the use of a separate adder module normally used in the conventional MACS thereby achieving approximate reductions of 50% and 20%, respectively, in the computation time and area making it attractive for VLSI implementation. It can be used as a fundamental computing block of the algorithmically specialized integrated circuits, like, systolic and wavefront array processors for an efficient implementation of the computationally intensive DSP functions: FIRDIR filtering, correlation, matrix multiplication etc., resulting in reduced hardware complexity and latency. The technology independent nature of the proposed architecture makes it attractive also for VLSI implementation using fast emerging contemporary technologies: GaAs (MESFET, HEMT, JET) and HBT.

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