Design and analysis of the dynamic frequency divider using the BiCMOS–NDR chaos-based circuit

Gan, Kwang–Jow; Guo, Chunyi; Wu, Ping-Feng; Chen, Yaw-Hwang

doi:10.1007/s10470-018-1200-y

Cited by 5 publications

(5 citation statements)

References 22 publications

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“…To demonstrate the frequency division, we perform the Runge-Kutta analyses again. By equation (8), to widen the frequency range succeeding in the frequency division having a common ratio, f 0 should be designed to become large. As aforementioned, a smaller L value tends to increase f 0 , provided the LC product is kept fixed.…”

Section: Frequency Division Using Td-oscillator Latticementioning

confidence: 99%

“…However, the integration of RTDs with FETs requires elaborate process and epitaxy technologies. Recently, the NDR circuit utilizing the BiCMOS technique is employed as the substitution for an RTD 8 . In addition, the RTD circuits with an optical/wireless interface 9 is investigated for their nonlinear dynamics including chaos and synchronization.…”

Section: Introductionmentioning

confidence: 99%

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A frequency divider using interacting self‐sustained pulses in a tunnel‐diode‐oscillator lattice

Narahara

2022

Circuit Theory & Apps

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Summary An effective method for frequency division, which uses interacting self‐sustained solitary waves propagating in a one‐dimensional tunnel‐diode oscillator lattice, is discussed. When two pulses are input successively, it is found that there is a threshold separation below which the following pulse is significantly attenuated to disappear on the way, which only slightly influences the leading pulse. This phenomenon results in an efficient frequency divider with a high division ratio, which requires a relatively small number of lattice cells. In this study, we illustrate the fundamental dynamics of the self‐sustained pulse interactions and principal operation of frequency division with several experimental validations.

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Section: Frequency Division Using Td-oscillator Latticementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A frequency divider using interacting self‐sustained pulses in a tunnel‐diode‐oscillator lattice

Narahara

2022

Circuit Theory & Apps

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“…The NDR concept has been researched for nearly 100 years [22,23,[26][27][28]. An NDR device is characterized by the negative slope of I-V curve.…”

Section: Cmos Ndrmentioning

confidence: 99%

“…4(b) [23,34]. The operating point B for intersecting at the NDR region is unstable [22]. If the current of the NDR-load is greater than current of the NDR-driver, the excess current must charge the load capacitance at the circuit output, so the output voltage increases.…”

Section: Neuron Transistormentioning

confidence: 99%

“…In the present research, the 180-nm United Microelectronics Corporation (UMC) standard complementary metal-oxide-semiconductor (CMOS) process is used to implement the basic functions of neurons (weighted sum and threshold). Based on our review of the literatures, these functions implemented using a commercial CMOS standard process based on negative differential resistance (NDR) theory [21][22][23] for the first time and can be integrated with other circuitry structures on the same chip. The NDR neuron transistor without a capacitance structure is measured at maximum frequency of 10 kHz, and the results indicate that it has an extremely low power consumption of <10 -4 μW.…”

Section: Introductionmentioning

confidence: 99%

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Silicon neuron transistor based on CMOS negative differential resistance (NDR)

Zhao

Cong

Guo

et al. 2020

IEICE Electron. Express

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Computer-science-oriented and neuroscience-oriented are two general approaches to developing artificial general intelligence (AGI). In this study, a silicon neuron transistor is developed using the neuroscience approach for AGI applications. Neuronal behavior ("weighted sum and threshold" function) is based on the complementary metal-oxidesemiconductor (CMOS) negative differential resistance (NDR) theory. The neuron transistor is implemented by the UMC 180-nm commercial standard CMOS process, which is beneficial to implement an entire neural network or integrate with other CMOS circuits on the same chip. The neuron transistor is composed of three inputs Vg1, Vg2, and Vg3 and one control terminal Vcon, Vb(load), and Vb(driver). The width of each input is 1.8 μm, and the inputs have 1, 2, and 4 fingers, that is, the weight ratio is 1:2:4. Vb(load) and Vb(driver) enable a neuron transistor to function more closely resembles a real biological neuron, with improved sensitivity and less complicacy compared to a traditional artificial neural network. The neuron MOS transistor was measured at the maximum frequency of 10 kHz. It had extremely low power consumption of <10-4 μW and a miniscule footprint 30 × 15 μm 2. As the process feature size decreases, the chip's operating frequency will increase by one order of magnitude, and its power consumption and footprint will decrease.

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Mackey–Glass Chaotic Time Series Forecasting by Using Self-Organizing Fuzzy Inference Network

Choe

Ri²,

Ryang³

et al. 2023

J. Inst. Eng. India Ser. B

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Design and analysis of the dynamic frequency divider using the BiCMOS–NDR chaos-based circuit

Cited by 5 publications

References 22 publications

A frequency divider using interacting self‐sustained pulses in a tunnel‐diode‐oscillator lattice

A frequency divider using interacting self‐sustained pulses in a tunnel‐diode‐oscillator lattice

Silicon neuron transistor based on CMOS negative differential resistance (NDR)

Mackey–Glass Chaotic Time Series Forecasting by Using Self-Organizing Fuzzy Inference Network

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