Design and Analysis of Power Efficient 64-Bit ALCCU

Abstract

Speed of any system depends on mainly two factors known as frequency and parllel processing. Such high speed processing systems are required in real time embedded systems. The existed systems are operated with maximum of 2 to 3 GHz. The proposed 64-bit ALCCU is a high-speed processing system that will perform arithmetic, logical and code conversion operations. It is implemented in structural style with Verilog Hardware Description Language. This design is a high speed, low powered and will perform 32 operations. Its data size is 64_bit, implemented on xc7a100tcsg324-1 which is an Artix 7, 100K gate technology FPGA with a CSG 324 package. Satisfactory low power (less than 1W) has been observed with varying clock rates of ranging from 10 MHz to 20 GHz. The analysis is done with Low Voltage CMOS I/O standards from 1.2 to 3.3V range. The application of the proposed design can be used as an IP in high speed processors and controllers.

Custom Ip Design and Verification for Ieee754 Single Precision Floating Point Arithmetic Unit

“…These constraints were applied to various input and output standards. The proposed system can be used as an IP [13] in high-speed controllers and processors. D.A.…”

“…The enhancement of the proposed work over the previous work is customized the design of FPAU in 28nm Technology. In the earlier work referred [13], [14], [15] and [16], the design is normal binary 32 bit and 64 bit arithmetic, logic and code conversion operations. All the works are verified with virtual input and output debug IP.…”

“…ii. In the reference [13], 64-bit arithmetic, logic, and code conversions are implemented with the Artix 7 FPGA and VIO hardware debug IP. iii.…”