Design and Analysis of MOSFET Based on Fan-out Panel-Level Package Technology

Zhi, Liang; Shao, Dongdong; Ding, Kunpeng; Tian, Chong‐Bin

doi:10.1109/icept52650.2021.9568028

2021 22nd International Conference on Electronic Packaging Technology (ICEPT) 2021

DOI: 10.1109/icept52650.2021.9568028

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Design and Analysis of MOSFET Based on Fan-out Panel-Level Package Technology

Liang Zhi¹,

Dongdong Shao²,

Kunpeng Ding³

et al.

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“…In this process, first, the die was attached to the lead frame, then RDL was performed after molding. Shao et al [26], [27] proposed single-die and dual-die MOSFETs with EMC-based FOPLP successively, realizing lower thermal resistance and ON-state resistance than wire-bonding structures. Due to the fewer and more convenient steps to finish die fixation, FOPLP using EMC exhibits lower costs and higher efficacy than PCB-embedded FOPLP.…”

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confidence: 99%

A Thin and Low-Inductance 1200 V SiC MOSFET Fan-Out Panel-Level Packaging With Thermal Cycling Reliability Evaluation

Chen

Jiang

Meda

et al. 2023

IEEE Trans. Electron Devices

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SiC MOSFET is mainly characterized by the higher electric breakdown field, higher thermal conductivity, and lower switching loss enabling high breakdown voltage, high-temperature operation, and high switching frequency. However, their performances are considerably limited by the high parasitic inductance and poor heat dissipation capabilities associated with existing wirebonding packaging methods. To address this challenge, a 1200 V/136 A fan-out panel-level packaging (FOPLP) SiC MOSFET with a size of 8 × 8 × 0.75 mm was proposed. The electrical parameters of the devices were characterized experimentally. Both the static and dynamic parameters of the package matched the bare die values, which confirmed the functioning of the proposed packaging method for SiC MOSFET. The package parasitic inductance, thermal resistance, and soldering stress were analyzed through simulations. The reliability of the packages was evaluated by performing the thermal cycling test. The

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confidence: 99%

A Thin and Low-Inductance 1200 V SiC MOSFET Fan-Out Panel-Level Packaging With Thermal Cycling Reliability Evaluation

Chen

Jiang

Meda

et al. 2023

IEEE Trans. Electron Devices

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Design and Analysis of MOSFET Based on Fan-out Panel-Level Package Technology

Cited by 1 publication

References 9 publications

A Thin and Low-Inductance 1200 V SiC MOSFET Fan-Out Panel-Level Packaging With Thermal Cycling Reliability Evaluation

A Thin and Low-Inductance 1200 V SiC MOSFET Fan-Out Panel-Level Packaging With Thermal Cycling Reliability Evaluation

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