Design and analysis of low power high-speed 1-bit full adder cells for VLSI applications

Tirumalasetty, Venkata Rao; Machupalli, Madhusudhan Reddy

doi:10.1080/00207217.2018.1545256

Cited by 27 publications

(28 citation statements)

References 13 publications

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“…As shown in Table 4, the proposed Hamming codes implementing using the FS-GDI achieves power e ciency 44.77% and 26.93% for the Hamming codes (7,4) and (11,7), respectively compared to the CMOS approach. While these proposed codes achieve delay time reduction by 52.91% and 10% for Hamming codes (7,4) and (11,7), respectively. These results clear the e ciency of the presented approach for implementing the different error control techniques.…”

Section: The Results Analysismentioning

confidence: 99%

“…The proposed approach for Hamming codes implementation achieves 50 % H/W simplicity. Also, the power e ciency of the proposed Hamming codes is improved by 44.77% and 26.93% for the Hamming codes (7,4) and (11,7), respectively compared to the CMOS approach. On the other hand, the delay time is optimized in the proposed Hamming codes implementation approach compared to the traditional CMOS approach.…”

Section: Discussionmentioning

confidence: 98%

“…In this section, the different Hamming codes (7,4) and (11,7) implementation approaches are presented. The FS-GDI approach are proposed for implementing the Hamming codes as an approach for achieving power e cient data encoding tool.…”

Section: The Proposed Scheme Descriptionmentioning

confidence: 99%

“…D 7 D 6 D 5 P 8 D 4 D 3 D 2 P 4 D 1 P 2 P 1 a. Performance Evaluating of the Proposed Hamming Encoder (11, 7) Design Table 3 shows the values of the evaluating metrics of the proposed implementing approach of Hamming code (11,7). As shown in the previous experiments which are devoted for evaluating the performance of the proposed design of the different Hamming codes with the various data-word and codeword lengths.…”

Section: The Proposed Fs-gdi Hamming Code (74) Design Implementingmentioning

confidence: 99%

“…In [11] the complexity in the wireless communications due to the amount of the transmitted data encoding is analyzed based on the used error control code is the Convolutional codes and the Hamming code. The presented analysis in this paper proved that the complexity is related to the amount of required/consumed power.…”

Section: Introductionmentioning

confidence: 99%

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Optimizing of Communications Systems Power Efficiency Considerations: Efficient Implementing Approach of Hamming Codes Utilizing FS-GDI

El‐Bendary

El-Badry

2021

Preprint

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Due to the power efficiency importance of digital signal processing and data protection in different communications systems, this paper proposes an efficient design of different Hamming Codes utilizing Full Swing- Gate Diffusion Input (FS-GDI) approach. The proposed codes design aims to improve the power efficiency and the required area through reducing the required number of transistors. FS-GDI is a new low power VLSI design approach, it is a power effective approach for realizing the different logic gates. In this work, the Hamming codes (7, 4) and (11, 7) are designed by utilizing the original GDI, FS-GDI and the traditional CMOS approaches. The amount of consumed power, delay time, Power Delay Product (PDP) and hardware simplicity-Number of Transistors (No.Ts) are employed as a metrics for evaluating the efficiency of the proposed design compared to the traditional design. The design simulation experiments are executed utilizing Cadence Virtuoso simulator package under 65nm technology. The simulation experiments revealed these proposed codes achieve delay time reduction by 52.91% and 10% for Hamming codes (7, 4) and (11, 7), respectively On the other hand, the Hardware (H/W) of these codes became more simple where the H/W simplicity of the used Hamming codes is reduced 50 % CMOS approaches respectively. From the results analysis, the proposed design achieves efficient power and the delay optimizing of Hamming codes utilizing the FS-GDI approach. On the other hand, the power consumption and area in communications systems due to the encoding process can be reduces.

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Section: The Results Analysismentioning

confidence: 99%

Section: Discussionmentioning

confidence: 98%

Section: The Proposed Scheme Descriptionmentioning

confidence: 99%

Section: The Proposed Fs-gdi Hamming Code (74) Design Implementingmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Optimizing of Communications Systems Power Efficiency Considerations: Efficient Implementing Approach of Hamming Codes Utilizing FS-GDI

El‐Bendary

El-Badry

2021

Preprint

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A scalable high‐speed hybrid 1‐bit full adder design using XOR‐XNOR module

Hasan

Islam

Hossain

et al. 2021

Circuit Theory & Apps

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High‐speed XOR‐XNOR‐based hybrid full adder (FA) using a combination of three logic techniques (transmission gate [TG], conventional CMOS [CCMOS], pass transistor [PT]) is presented in this work. Performance analysis and validation of the FA design presented in this work have been realized with reference to 10 state‐of‐the‐art FAs. The scalability of the design has been tested by extending FA up to 32‐bits in ripple carry adder (RCA) style. It has been observed that only four existing FAs and the proposed FA could be scaled up to 32‐bits without including voltage restoration buffers in the internal stages. The proposed XOR‐XNOR‐based FA showed excellent performance metrics, both as a 1‐bit adder cell as well as in wide word length adder form. Hence, the proposed XOR‐XNOR‐based hybrid FA can serve as a better alternative to the existing FAs in digital arithmetic blocks of modern microprocessors.

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Design of 1-Bit FinFET Sum Circuit for Computational Applications

Pittala¹,

Vijay

2021

Advanced Techniques for IoT Applications

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Design and analysis of low power high-speed 1-bit full adder cells for VLSI applications

Cited by 27 publications

References 13 publications

Optimizing of Communications Systems Power Efficiency Considerations: Efficient Implementing Approach of Hamming Codes Utilizing FS-GDI

Optimizing of Communications Systems Power Efficiency Considerations: Efficient Implementing Approach of Hamming Codes Utilizing FS-GDI

A scalable high‐speed hybrid 1‐bit full adder design using XOR‐XNOR module

Design of 1-Bit FinFET Sum Circuit for Computational Applications

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