Design and Analysis of Gate Engineered Dual Material Gate Double Gate Impact Ionization Metal Oxide Semiconductor

Solay, Leo Raj; Singh, Sarabdeep; Amin, S. Intekhab; Anand, Sunny

doi:10.1007/s42341-018-0080-2

Cited by 13 publications

(5 citation statements)

References 19 publications

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“…The total gate capacitance (C GG ) is shown against the gate voltage in figure 4(a). The sum of the gate-to-source (C GS ) and gateto-drain (C GD ) capacitances yields the total gate capacitance (C GG ) as specified in equation (6).…”

Section: Resultsmentioning

confidence: 99%

“…MOSFETs are less appropriate for analog and sensing applications due to their low current ratio (I ON /I OFF ), low intrinsic gain (A v ), higher OFF-current (I OFF ), and low unity gain frequency (F T ) [3]. Several proposed devices, including tunnel field effect transistors (TFETs) [4], nano-electromechanical field effect transistors [5], and impact ionization MOS [6], have promising features such as low subthreshold swing (SS) and high I ON /I OFF ratio. TFETs are the next best alternative device [7] for transistor downscaling with reduced SCEs.…”

Section: Introductionmentioning

confidence: 99%

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Design and performance analysis of gate-all-around negative capacitance dopingless nanowire tunnel field effect transistor

Solay

Kumar²,

Amin³

et al. 2022

Semicond. Sci. Technol.

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In this paper, a novel low power consumption device based on dopingless gate all around nanowire tunnel field effect transistor with negative capacitance effect is proposed. Negative capacitance is a robust approach in solving the bottleneck issues encountered by devices operating in nanoscale domains. Additionally, VT and SS are dropped significantly to less than 60mV/decade. Negative capacitance makes significant contribution to the device performance by lowering operating voltage for low power applications. To calculate the optimum bias, Landau-Khalatnikov (L-K) equation has been used. To evaluate the influence of negative capacitance, ferroelectric (FE) material PZT (lead zirconate titanate) – ceramic material which has perovskite properties has been used as gate insulator. Thus, gate all around dopingless nanowire TFET (GAA DL NW TFET) device structure is reconfigured into GAA negative capacitance DL NW TFET (GAA NC DL NW TFET). PZT has an appropriate polarization rate, high dielectric capacitance and high degree of reliability. To achieve SS lower than 60mV/decade at lower VT, effective tuning of FE thickness is critical to avoid hysteresis, which enhances the overall performance of the proposed device structure. Aggressively scaled device has the problem of fabrication complexity and its associated cost that is addressed with the help of doping-less technique to the nanowire based TFET. The enhancement of the on-state current at reduced supply voltage of silicon based TFET devices with improved steep subthreshold swing which has been addressed with the help of NC technique. With the application of NC technique, the proposed device showcased an improved 4 (µA/µm) of ION, 1012 of current ratio. Additionally, influence of variation in FE thickness (tFE) on performance parameters are examined. The proposed device structure, GAA NC DL NW TFET operates at minimum operating voltage than GAA DL NW TFET making it as an ideal choice for low power voltage applications

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Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Design and performance analysis of gate-all-around negative capacitance dopingless nanowire tunnel field effect transistor

Solay

Kumar²,

Amin³

et al. 2022

Semicond. Sci. Technol.

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“…To surpass the SCEs, devices like Tunnel-FET (TFETs) [13][14], Impact Ionization MOS (IMOS) [15] and novel structured designs such as three-dimensional (3D) structures [16], multi-gate designs such as tri-gate structures [17][18] for improved controllability over gate and gate-all-around (GAA) structure designs with high packaging density and excellent gate controllability over the channel were considered as the best replacements [19]. With the applications include clinical purpose biosensors [20], industrial based pressure sensors [21] etc.…”

Section: Introductionmentioning

confidence: 99%

Investigation of Common Source Amplifier Circuit Application Using Gate Stack Based Gate-all-around Charge Plasma Nanowire FET

Solay¹,

Kumar²,

Amin

et al. 2022

Preprint

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The reported work demonstrates the application of common source amplifier circuit using gate-all-around gate stacked charge plasma nanowire field effect transistor (GAA GS CP NW FET). Primarily, the impact of the gate stacking (GS) technique upon the Gate-All-Around Charge Plasma Nanowire Field Effect Transistor (GAA CP NW FET) structure is explored. In which GAA GS CP NW FET structure resulted in excellent electrostatic control over the channel by incorporating the advantages of GAA structures. The transfer characteristics have been enhanced with the gate stacking (SiO2 + high k) technique when employed at the dielectric region of the structure. The charge plasma concept which is applied in the proposed device helped in reducing the threshold voltage fluctuations. A contrast is drawn between GAA CP NW FET and GAA GS CP NW FET structures in terms of analog and RF analysis. Linearity parametric analysis were made to examine the distortion less digital communication and a comparison is made between the structures. The proposed structure is then utilized for designing a common source amplifier circuit and contrasted with the GAA CP NW FET structure. With the applied gate stacking technique, the proposed structure resulted in improved ON-current, reduced OFF-current, enhanced current ratio. The CS amplifier circuit application resulted in improved Vout and gain attributes with the proposed GAA GS CP NW FET structure when compared with Metal Oxide Semiconductor FET (MOSFET), Tunnel FET (TFET) and GAA CP NW FET structure proving its capability for forthcoming nanoscale circuit applications.

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“…With the ongoing scaling or miniaturization of devices, it becomes increasingly difficult to follow Moore's law when the technology scale decreases below physical limits [6]. Indeed, Moore's law can only hold true down to a certain degree of scaling, while next-generation electron devices will be required to achieve further downscaling because of the need to boost performance with reduced power consumption [7]. Below the 100-nm regime, device scaling results in fundamental issues associated with the performance characteristics of MOS field-effect transistors (MOSFETs), including the ON-current, power consumption, and short-channel effects (SCEs) [8].…”

Section: Introductionmentioning

confidence: 99%

Enhancing the design and performance of a gate-all-around (GAA) charge plasma nanowire field-effect transistor with the help of the negative-capacitance technique

et al. 2021

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A gate-all-around charge plasma nanowire field-effect transistor (GAA CP NW FET) device using the negative-capacitance technique is introduced, termed the GAA CP NW negative-capacitance (NC) FET. In the face of bottleneck issues in nanoscale devices such as rising power dissipation, new techniques must be introduced into FET structures to overcome their major limitations. Negative capacitance is an efficient effect that can be incorporated into a device to enhance its performance for low-power applications and help to reduce the operating voltage. The Landau-Khalatnikov equation can be applied in such cases to obtain the effective bias. To determine the effects of negative capacitance, lead zirconate titanate (PZT) ferroelectric material, a ceramic material with perovskite properties, is adopted as a gate insulator. This approach diminishes the supply voltage and reduces the power dissipation in the device. Excluding their polarization properties, ferroelectric materials are similar to dielectric materials, and PZT offers abundant polarization with improved reliability and a higher dielectric capacitance. Without proper tuning of the thickness of the PZT material, hysteresis behavior mat occur. Hence, the thickness of the PZT material (t FE ) is an essential parameter to optimize the device performance and achieve a reduced threshold voltage for the GAA CP NW NC-FET device proposed herein. Furthermore, varying the thickness of the PZT ferroelectric material can also enhance the performance. When using the highest values of t FE , improved outcomes with an analogously lower operating voltage are observed. The effects of varying t FE on the performance characteristics of the device including the drain current, transconductance, polarized charge, etc. are also interpreted herein.

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Design and Analysis of Gate Engineered Dual Material Gate Double Gate Impact Ionization Metal Oxide Semiconductor

Cited by 13 publications

References 19 publications

Design and performance analysis of gate-all-around negative capacitance dopingless nanowire tunnel field effect transistor

Design and performance analysis of gate-all-around negative capacitance dopingless nanowire tunnel field effect transistor

Investigation of Common Source Amplifier Circuit Application Using Gate Stack Based Gate-all-around Charge Plasma Nanowire FET

Enhancing the design and performance of a gate-all-around (GAA) charge plasma nanowire field-effect transistor with the help of the negative-capacitance technique

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