Design and Analysis of Efficient Maximum/Minimum Circuits for Stochastic Computing

Abstract

In stochastic computing (SC), a real-valued number is represented by a stochastic bit stream, encoding its value in the probability of obtaining a one. This leads to a significantly lower hardware effort for various functions and provides a higher tolerance to errors (e.g., bit flips) compared to binary radix representation. The implementation of a stochastic max/min function is important for many areas where SC has been successfully applied, such as image processing or machine learning (e.g., max pooling in neural networks). In this work, we propose a novel shift-register-based architecture for a stochastic max/min function. We show that the proposed circuit has a significantly higher accuracy than state-of-the-art architectures at comparable hardware cost. Moreover, we analytically proof the correctness of the proposed circuit and provide a new error analysis, based on the individual bits of the stochastic streams. Interestingly, the analysis reveals that for a certain practical bit stream length a finite optimal shift register length exists and it allows to determine the optimal length.

A Stochastic Computing Architecture for Iterative Estimation

“…If A represents a larger number than B, ones of A in excess to B are output as well, together representing the number of bitstream A (then the maximum) in the output stream. As described in [22], this circuit closely approximates the maximum function with high precision, with its error depending on the shift register length as well as of course on the bitstream length.…”

“…In the literature, several min/max circuits for stochastic computing have been proposed [20]- [22]. The approach of [22], as depicted on the right in Fig.…”

“…In the literature, several min/max circuits for stochastic computing have been proposed [20]- [22]. The approach of [22], as depicted on the right in Fig. 2, not only provides a higher precision compared to the other proposed circuits, but also shows an important property for implementing the shrink function: the ones of input stream B are always output by the circuit.…”

A Stochastic Logic-Based Fuzzy Logic Controller: First Experimental Results of a Novel Architecture

“…The cost of the aforementioned attributes is a trade-off between precision and latency in signal representations, since the longer the processed bit stream the higher precision is achieved. For the relaxation of this tradeoff novel processing methods are proposed in the literature, which aim to both exploit the advantageous features and overcome the difficulties of this computing paradigm [13], [14], [15].…”

“…It is worth mentioning that the XOR gate is also employed for similar arithmetic operations [13]. Namely, if the input stochastic bit streams X 1 and X 2 are unequal, then the XOR gate produces 1 at its output, i.e.…”