Design and Analysis of DTC-Free ΔΣ Bang-Bang Phase-Locked Loops

Abstract

This paper discusses different design aspects of the ∆Σ fractional-N bang-bang PLL (BBPLL) compared with conventional analog or digital fractional-N PLLs performing linear phase detection. Several in-band noise reduction methods without relying on a high-performance digital-to-time converter (DTC) are considered at the architecture-level. It is shown that two-stage topology, single-bit ∆Σ modulation, and phase-domain filtering methods can improve the in-band phase noise, which is different from the conventional PLLs. It is also shown that two-point modulation is superior to one-point modulation regardless of data rate when an overdamped BBPLL is employed for frequency modulation. By integrating those in-band noise reduction methods, we propose a DTC-free, calibration-free ∆Σ BBPLL architecture that achieves the inband noise of about -100dBc/Hz. Behavioral simulation results show that the in-band noise performance can be improved by nearly 40dB without having the DTC.