Design and analysis of buffer and bufferless routing based NoC for high throughput and low latency communication on FPGA

Sujata, S. B.; Sandi, Anuradha M.

doi:10.1108/ijpcc-05-2021-0115

Cited by 5 publications

(1 citation statement)

References 27 publications

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“…Each step in a scalable node network has a router to manage the usage of shared resources [25]. The typical NoC router functions as shown below.…”

Section: B the Router Designsmentioning

confidence: 99%

Design and Implementation of High QoS 3D-NoC using Modified Double Particle Swarm Optimization on FPGA

S. B.,

M. Sandi

2023

IJRITCC

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One technique to overcome the exponential growth bottleneck is to increase the number of cores on a processor, although having too many cores might cause issues including chip overheating and communication blockage. The problem of the communication bottleneck on the chip is presently effectively resolved by networks-on-chip (NoC). A 3D stack of chips is now possible, thanks to recent developments in IC manufacturing techniques, enabling to reduce of chip area while increasing chip throughput and reducing power consumption. The automated process associated with mapping applications to form three-dimensional NoC architectures is a significant new path in 3D NoC research. This work proposes a 3D NoC partitioning approach that can identify the 3D NoC region that has to be mapped. A double particle swarm optimization (DPSO) inspired algorithmic technique, which may combine the characteristics having neighbourhood search and genetic architectures, also addresses the challenge of a particle swarm algorithm descending into local optimal solutions. Experimental evidence supports the claim that this hybrid optimization algorithm based on Double Particle Swarm Optimisation outperforms the conventional heuristic technique in terms of output rate and loss in energy. The findings demonstrate that in a network of the same size, the newly introduced router delivers the lowest loss on the longest path. Three factors, namely energy, latency or delay, and throughput, are compared between the suggested 3D mesh ONoC and its 2D version. When comparing power consumption between 3D ONoC and its electronic and 2D equivalents, which both have 512 IP cores, it may save roughly 79.9% of the energy used by the electronic counterpart and 24.3% of the energy used by the latter. The network efficiency of the 3D mesh ONoC is simulated by DPSO in a variety of configurations. The outcomes also demonstrate an increase in performance over the 2D ONoC. As a flexible communication solution, Network-On-Chips (NoCs) have been frequently employed in the development of multiprocessor system-on-chips (MPSoCs). By outsourcing their communication activities, NoCs permit on-chip Intellectual Property (IP) cores to communicate with one another and function at a better level. The important components in assigning application duties, distributing the work to the IPs, and coordinating communication among them are mapping and scheduling methods. This study aims to present an entirely advanced form of research in the area of 3D NoC mapping and scheduling applications, grouping the results according to various parameters and offering several suggestions for further research.

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“…Each step in a scalable node network has a router to manage the usage of shared resources [25]. The typical NoC router functions as shown below.…”

Section: B the Router Designsmentioning

confidence: 99%

Design and Implementation of High QoS 3D-NoC using Modified Double Particle Swarm Optimization on FPGA

S. B.,

M. Sandi

2023

IJRITCC

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Design and implementation of network‐on‐chip router using multi‐priority based iterative round‐robin matching with slip

Singh

Ravindra²,

Naik

2022

Trans Emerging Tel Tech

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Nowadays, network‐on‐chip (NoC) routers become important in several applications including mobile technology and digital communication. Multiple cores/processors are typically coupled using NoC routers, which considerably improve integrated circuit performance in terms of power, latency, throughput, and area. So, a novel 4 × 4 topology‐based NoC router using multi‐priority based iterative round‐robin matching with slip (MPiSLIP) routing algorithm is implemented in this work. The proposed work contains different operational blocks classification such as route computation using static straight allocator, route controlling using MPiSLIP arbiter, a crossbar switch, combined parallel virtual channel and switch allocation unit, look ahead bypass route computation (LBRC), and input‐output ports. The MPiSLIP routing mechanism also determines the priorities necessary for route development. Finally, by bypassing the switches and fulfilling all of the priories in a look‐ahead manner, LBRC is employed to establish the effective path between input ports and output ports. The simulation results show that the proposed MPiSLIP‐based NoC routing method resulted in a reduced area, power, and latency as compared to the open‐source NoCs, multi‐processor NoCs, multi‐core NoCs, and conventional routing algorithms.

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Time Synchronized Sensor Network with IEEE1588 for Vibration Measurement in Structural Health Monitoring of Railway System

Jiang,

Liu,

et al. 2024

Lecture Notes in Electrical Engineering

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Design and analysis of buffer and bufferless routing based NoC for high throughput and low latency communication on FPGA

Cited by 5 publications

References 27 publications

Design and Implementation of High QoS 3D-NoC using Modified Double Particle Swarm Optimization on FPGA

Design and Implementation of High QoS 3D-NoC using Modified Double Particle Swarm Optimization on FPGA

Design and implementation of network‐on‐chip router using multi‐priority based iterative round‐robin matching with slip

Time Synchronized Sensor Network with IEEE1588 for Vibration Measurement in Structural Health Monitoring of Railway System

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