Design and Analysis of Area and Power Efficient Approximate Booth Multipliers

Venkatachalam, S.; Adams, Elizabeth; Lee, Hyuk Jae; Ko, Seok‐Bum

doi:10.1109/tc.2019.2926275

Cited by 96 publications

(49 citation statements)

References 19 publications

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“…But, this scheme suffers from the problems of weak 1/strong 0 and the signal paths are not balanced. Research [22] provided three approximation techniques for radix-4 Booth multipliers and one of them is called approximate Booth multipliers models 1 (ABM-M1). ABM-M1 is composed of the exact partial product generators (radix-4 Booth encoder and encoder) and the approximate 2signal partial product generators (called PPG-2S).…”

Section: B Related Workmentioning

confidence: 99%

“…The traditional design [16] The neg-first design [18] The NMBE design [19] The ABM-M1 design [22] The proposed design implemented easily by an NMOS. Like the proposed encoder, the proposed decoder adopts the gating techniques.…”

Section: Comparisons For the Radix-4 Booth Algorithmsmentioning

confidence: 99%

“…The proposed design is simulated with Taiwan Semiconductor Manufacturing Company (TSMC) 40 nm technology. Compared with the traditional design [16] and the related designs [18], [19], [22], the simulation results show that the proposed design outperforms these designs in terms of transistor count, delay, and power consumption.…”

Section: Introductionmentioning

confidence: 99%

“…For some error-tolerant applications, the approximate circuits can be employed to achieve low power, low circuit complexity, and high performance [9], [20] - [22]. The traditional radix- 8 x x 7 6 x x 6 5 x x 5 4 x x than the radix-4 Booth algorithm, but it needs additional adders to process the operation of odd multiples of the multiplicand.…”

Section: Introductionmentioning

confidence: 99%

“…In [21], the approximate radix-4 Booth multipliers were proposed by using their approximate Booth encoders and approximate Wallace tree structure. In [22], three approximation techniques for the radix-4 Booth multiplier were proposed and these designs can reduce the logic complexity of the PP generator.…”

Section: Introductionmentioning

confidence: 99%

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A Low Power Radix-4 Booth Multiplier With Pre-Encoded Mechanism

et al. 2020

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The radix-4 Booth algorithm is widely used to improve the performance of multiplier because it can reduce the number of partial products by half. However, numerous additional encoders and decoders would cause the power consumption of the Booth multiplier to be considerable. In this paper, a new radix-4 Booth pre-encoded mechanism is proposed to reduce the power consumption of the Booth multiplier. The proposed design can effectively reduce the power of the Booth multiplier dissipated in the redundant activities by disabling the Booth encoders and decoders from unnecessary working. Particularly, since the control signals are generated early at the pipeline input register before the multiplier, the performance of our design is better than the traditional Booth multiplier. Based on the TSMC 40 nm technology, the simulation results show that the proposed pre-encoded mechanism can reduce the dynamic and static power by 45% and 65%, respectively, compared to the traditional 16-bit radix-4 Booth multiplier. Compared to the previous designs, the proposed design keeps the feature of race-free and has lower power consumption. Even compared to the approximate design, the proposed design has better power efficiency and can provide the exact products.

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Section: B Related Workmentioning

confidence: 99%

Section: Comparisons For the Radix-4 Booth Algorithmsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A Low Power Radix-4 Booth Multiplier With Pre-Encoded Mechanism

et al. 2020

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A new high speed and low power decoder/encoder for Radix‐4 Booth multiplier

Ghasemi

Fathi

Mousazadeh

et al. 2021

Circuit Theory & Apps

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SummaryThe proposed booth decoder/encoder unit is an ultrahigh‐speed unit among the reported ones which was designed by modifying and creating a new format truth table with 0.18 μm CMOS technology. According to the modified truth table, four cases are defined, and a proper circuit for each case is designed. The proposed structure is discussed considering the possible problems such as the swing and discharge problems. The gate‐level delay of the proposed structure and other related works have been calculated and are compared. The propagation delay of the proposed structure has been calculated and simulated to validate the data. To justify the comparisons, other related works have been simulated again with the same condition. The propagation delay of the proposed structure is 226 ps, which is minimum compared to previous related works. The proposed structure reduces the delay by 30–200% comparing related works and also improves the delay of the multiplier 4–21%. The power consumption and the area of the structure are 477 μw and 20 × 18 μm2, respectively. In this paper, Hspice software for simulating, MATLAB for numerical calculations, and Cadence for designing the layout of the proposed structure have been used.

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Energy efficient approximate booth multipliers using compact error compensation circuit for mitigation of truncation error

Aizaz

Khare

2022

Circuit Theory & Apps

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Artificial neural networks and image processing are the error tolerant applications that require massive workloads to be executed within certain power limits. Energy efficient multipliers on an embedded processor are crucial for such applications. In this paper, a highly diminished yet accurate design of an approximate truncated multiplier is presented. A compact error compensation circuit is presented that aims to mitigate the truncation error. To reduce the energy consumption further, the voltage overscaling method is used. The performance of the circuit is optimized by adjusting the two approximation knobs of circuit pruning and voltage scaling. Simulation results for a truncation factor of 8 with an MRED of 0.01 demonstrate an 11.4% reduction in energy consumption compared to that of the 16‐bit radix‐4 exact multiplier. Application based evaluation is performed by using the approximate multipliers on image multiplication application and a high value of PSNR (43.17 dB) is obtained. When evaluated using a handwritten digit recognition application based on convolutional neural networks (CNN), an accuracy of 97.85% is obtained.

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Design and Analysis of Area and Power Efficient Approximate Booth Multipliers

Cited by 96 publications

References 19 publications

A Low Power Radix-4 Booth Multiplier With Pre-Encoded Mechanism

A Low Power Radix-4 Booth Multiplier With Pre-Encoded Mechanism

A new high speed and low power decoder/encoder for Radix‐4 Booth multiplier

Energy efficient approximate booth multipliers using compact error compensation circuit for mitigation of truncation error

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