Design and Analysis of Approximate Compressors for Multiplication

Abstract

Inexact (or approximate) computing is an attractive paradigm for digital processing at nanometric scales. Inexact computing is particularly interesting for computer arithmetic designs. This paper deals with the analysis and design of two new approximate 4-2 compressors for utilization in a multiplier. These designs rely on different features of compression, such that imprecision in computation (as measured by the error rate and the so-called normalized error distance) can meet with respect to circuit-based figures of merit of a design (number of transistors, delay and power consumption). Four different schemes for utilizing the proposed approximate compressors are proposed and analyzed for a Dadda multiplier. Extensive simulation results are provided and an application of the approximate multipliers to image processing is presented. The results show that the proposed designs accomplish significant reductions in power dissipation, delay and transistor count compared to an exact design; moreover, two of the proposed multiplier designs provide excellent capabilities for image multiplication with respect to average normalized error distance and peak signal-to-noise ratio (more than 50dB for the considered image examples).

High Performance 8-bit Approximate Multiplier using Novel 4:2 Approximate Compressors for Fast Image Processing

“…The general form of a 4:2 compressor (a) with input carry, (b) without input carry [15]. In each of the 4:2 approximate compressors proposed in [15] and [16], the input carry was supposed to be zero. Therefore, the input carries were removed from their input list.…”

“…Fig. 4 depicts two special implementations of the mentioned approximate compressors [15,16]. Table 1 shows the truth tables of these two circuits.…”

“…According to these tables, the MSE of each of these two compressors is 0.25. [15], and (b) [16]. [15], and (b) [16].…”

“…[15], and (b) [16]. [15], and (b) [16]. The difference column indicates the difference between the output of approximate and precise compressors.…”

“…Therefore, to increase the speed, the sum of S and the error signal were computed approximately by using only some orgates instead of some half and full-adders. In each of [15] and [16], a 4:2 approximate compressor with the mean square error (MSE) of 0.25 was proposed and then each one was used to design a fast 8-bit Dadda multiplier. The delay of each of these two 4:2 approximate compressors is less than that of 4:2 precise compressors.…”