Design and Analysis of Analog to Digital Converter System Clock Source Using Direct Digital Synthesizer

Abstract

A requirement of multiple format standards by mobile telecommunication (GSM, CDMA, WCDMA, and TD-SCDMA) test set needs to be delivered possibly at lower cost. As to support its capability, phase-locked loop (PLL) frequency synthesizer has been designated as an essential part in most of the design within the box. The old design may be bulky and subject to many issues with the components' variation and aging effect. In recent years, the direct digital synthesizer (DDS) has been popularly in used to replace the PLL architecture. This chapter will focus on the DDS selection, architecture topology, prototyping, implementation technique with both hardware and software, and performance as a clock source to a sampled system as referred to receiver interest. The key parameters in the sampled system greatly rely on the jitter and phase noise specification. If they are not properly defined, the overall signal-to-noise ratio (SNR) at the sampled system output will be impacted. Eventually the receiver quality will be degraded and resulted in tremendous loss. Thus, a proper reconstruction filter design will be delivered to ensure the jitter and phase noise performance is met without degrading the existing specification by taking accountability into the matching characteristic and signal integrity.