Design and Analysis of an Adaptively Biased Low-Dropout Regulator Using Enhanced Current Mirror Buffer

Abstract

This paper presents an adaptively biased, low dropout regulator (AB-LDR) using an enhanced current mirror (ECM) buffer for effectively driving the gate of the PMOS power transistor. The proposed ECM buffer offers very low output impedance which pushes out the pole at the gate of the PMOS power transistor to improve the stability. At the same time, it offers a symmetric pull-up/down slew rate to enhance the speed of the buffer, whenever the regulator is under large signal operation during the load transient. Moreover, the ECM buffer is modified to develop the regulator topology without introducing an error amplifier as a separate independent stage. It helps to minimize the overall quiescent current consumption at low load condition and makes frequency compensation easier. Finally, the speed of the adaptive bias loop (ABL) is increased by avoiding the highly capacitive gate node of the PMOS power transistor. A comprehensive small signal analysis of the proposed regulator is also carried out for a clear understanding of the stability of each loop considering the interaction of the other loop. The regulator is implemented in a 0.18 µm CMOS technology with a quiescent current of 900 nA. A maximum transient output voltage variation of 2.1% is observed with C o =470 nF. Index Terms-Low dropout regulator, current mirror, voltage buffer, main feedback loop, adaptive bias loop. 0885-8993 (c)

Analysis, Design, and Performance Evaluation of a Dynamically Slew Enhanced Adaptively Biased Capacitor-Less Low Dropout Regulator

“…Content may change prior to final publication. Under matched condition and assuming C 1 = C 2 , different transfer functions of the sub-blocks are given in (13)(14)(15)(16)(17)(18)(19).…”

“…A capacitor-less low dropout regulator (CL-LDR) is an ideal choice for that, as it saves extra off-chip component count and board space [9]- [13]. The transient response of any regulator mainly depends on the loop bandwidth and the slew rate at the gate of the PMOS pass transistor [14]- [16]. Recently, [17] proposes a dynamically slew enhanced adaptive bias (DSE-AB) scheme for an externally compensated, with-capacitor low dropout regulator (WC-LDR) to reduce the response time as well as the undershoot and overshoot without increasing the quiescent current I Q .…”

A novel active‐input cascode current mirror with high precision and low power dissipation

“…A current mirror (CM) is a unity gain current amplifier which replicates proportionally the input current at its high impedance output node. It is widely adopted as one of the most critical blocks in integrated analog or mixed‐signal circuits such as current‐mode A/D converters, 1–3 low‐dropout regulator, 4–6 operational amplifiers, 7,8 voltage level shifter, 9–11 and analog filters 12,13 and so forth. Therefore, the performances of CMs could directly influence system performances 14 .…”

Design and realization of low dropout voltage regulators in PMIC for portable applications

“…[63], [16], [64], [38]. However, many of them find limitations in system-on-chip (SoC) battery-powered portable commercial applications, where the output load current can be 1 A or more with very stringent requirements on DC voltage variation and transient load current variations.…”

“…From (1), the LDO output overshoot or undershoot ∆𝑉 𝑜 is largely proportional to ∆𝐼 𝐿 . In order to achieve a small ∆𝑉 𝑜 , the LDO needs to be designed with small 𝑇 𝑟 and/or large 𝐶 𝐿 , [9], [38], [76], [77]. However, these two solutions are arguably impractical for modern mobiles because the former typically relies on the large power dissipation of the LDO, and the later causes undesirable increase in device form factor [77], [78], [22], [21].…”