Design and Analysis of a Delay Sensor Applicable to Process/Environmental Variations and Aging Measurements

Wang, Xiaoxiao; Tehranipoor, Mohammad; George, Saji; Tran, Dat; Winemberg, LeRoy

doi:10.1109/tvlsi.2011.2158124

Cited by 39 publications

(13 citation statements)

References 22 publications

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“…In the first approach the absolute measurement of path delay is achieved using either a Time-to-Digital Converter (TDC) to translate timing information into digital values [12]- [15], or time-to-voltage conversion to translate path delay into voltage levels [16]. In the second approach ad-hoc sampling elements replace latches or flip-flops in the critical paths of the circuit.…”

Section: Background On Detection and Correction Paradigmmentioning

confidence: 99%

A cross-level verification methodology for digital IPs augmented with embedded timing monitors

Guarnieri

Petricca

Sassone

et al. 2014

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2014

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Smart systems implement the leading technology advances in the context of embedded devices. Current design methodologies are not suitable to deal with tightly interacting subsystems of different technological domains, namely analog, digital, discrete and power devices, MEMS and power sources. The effects of interaction between components and with the environment must be modeled and simulated at system level to achieve high performance. Focusing on the digital domain, additional design constraints have to be considered as a result of the integration of multi-domain subsystems in a single device. The main digital design challenges, combined with those emerging from the heterogeneous nature of the whole system, directly impact on performance and on propagation delay of the digital component. This paper proposes a design approach to enhance the RTL model of a given digital component for the integration in smart systems, and a methodology to verify the added features at system-level. The design approach consists of augmenting the RTL model through the automatic insertion of delay sensors, which can detect and correct timing failures. The augmented model is abstracted to SystemC TLM and, then, mutants (i.e., code mutations for emulating timing failures) are automatically injected into the model. Experimental results demonstrate the applicability of the proposed design and verification methodology and the effectiveness of the simulation performance.

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Section: Background On Detection and Correction Paradigmmentioning

confidence: 99%

A cross-level verification methodology for digital IPs augmented with embedded timing monitors

Guarnieri

Petricca

Sassone

et al. 2014

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2014

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“…In the Path-RO architecture [15] path delays are converted into oscillation frequencies that are read out through a counter. A calibration process is used to increase the accuracy over TDCs that typically assume a negligible or deterministically bounded timing impact of the measurement circuit.…”

Section: Related Workmentioning

confidence: 99%

“…The need of such dynamic monitoring of performance has spurred a vast amount of literature concerned with the implementation of embedded delay monitors with the most diverse characteristics [5], [8], [10], [12], [15], [17]. All these implementations are useful in different ways depending on the true objective of the measurement.…”

Section: Introductionmentioning

confidence: 99%

A fully standard-cell delay measurement circuit for timing variability detection

Sassone¹,

Petricca²,

Poncino³

et al. 2013

2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)

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With the scaling of CMOS technology, critical paths in digital circuits have become largely sensitive to process, voltage and temperature variations as well as to aging effects, generally resulting into a mismatch between the simulated path delay of the circuit obtained with CAD tools and the actual path delay on the manufactured chip. In order to solve this issue and to also avoid conservative strategies based on increasing time margins, adaptive techniques are the most desirable solution because they should automatically sense and correct timing variations online. Implementing such adaptive strategies requires accurate, high resolution and compact delay measurement devices. In this work we propose an effective, fully-digital, online delay measurement circuit that can be entirely implemented in a standard cell technology without the need of custom elements. Our design provides low-cost multi-paths delay monitoring while achieving high accuracy of the measurements (in the order of 30ps).

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“…RO-based structures are widely used as they are easy to implement and measure and valuable for correlating technology to circuit performance. A critical path RO, created by connecting the critical path output back to the input, can be assessed for aging effects by monitoring its frequency drift and can serve for both characterization and sensor purposes [5]. Furthermore, the RO can be designed in different configurations to effectively separate different aging mechanisms and use beat frequency detection to improve resolution by minimizing common mode noise [6].…”

Section: Previous Workmentioning

confidence: 99%

Asymmetric Aging and Workload Sensitive Bias Temperature Instability Sensors

Chen

Reddy

Krishnan

et al. 2012

IEEE Des. Test. Comput.

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Design and Analysis of a Delay Sensor Applicable to Process/Environmental Variations and Aging Measurements

Cited by 39 publications

References 22 publications

A cross-level verification methodology for digital IPs augmented with embedded timing monitors

A cross-level verification methodology for digital IPs augmented with embedded timing monitors

A fully standard-cell delay measurement circuit for timing variability detection

Asymmetric Aging and Workload Sensitive Bias Temperature Instability Sensors

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