Design and analysis of a SET tolerant single-phase clocked double-tail dynamic comparator

Wu, Hao; Jin, Gang; Zhang, Yiqi

doi:10.1007/s10470-022-02054-7

Cited by 1 publication

(2 citation statements)

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“…Because of the autozeroing technique used in [11] the input offset is low, but the SET tolerance only limits errors to a single clock cycle rather than working to entirely prevent SET errors. The performance of [14] struggles with input offset due to the many additional transistors in the modified latch increasing mismatch. The proposed design also has a large input offset; fortunately, well established offset cancellation techniques can be applied to reduce the impact of mismatch.…”

Section: B Simulation Resultsmentioning

confidence: 99%

“…Under normal conditions, the split path circuit behaves identically to the original; however, during SETs, there is an alternative path for current to continue to flow. Recently [14] moved radiationhardened comparator design forward by improving a doubletail dynamic comparator with a radiation-hardened latch. SETs on most nodes could be quickly cleared from the system by additional paths in the latch capable of forcing faulty voltages back to the proper state.…”

Section: B Radiation Hardening By Designmentioning

confidence: 99%

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A Single-Event Transient (SET) Tolerant Dynamic Bias Comparator in 65-nm CMOS

Ash,

2023

2023 IEEE 66th International Midwest Symposium on Circuits and Systems (MWSCAS)

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A single-event transient (SET) tolerant dynamic bias comparator leveraging path-splitting is presented in this paper. The dynamic bias structure with a tail capacitor is found to be vulnerable to positive and negative SET transients. A negative transient on the tail transistor doubles the energy per conversion. A positive transient on the tail MOS capacitor reduces the preamplifier gain by 35.7%, which increases the metastability error rate in the subsequent latch. A path splitting technique is applied to mitigate the positive SET. Simulations in a 65nm CMOS process showed that a two path split can recover the comparator output voltage swing by 12.7%. Compared with the state-of-the-art CMOS radiation-hardened by design (RHBD) dynamic comparators, this circuit achieved the lowest energy per comparison while maintaining low input referred noise and gaining SET tolerance in the evaluation phase.

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Section: B Simulation Resultsmentioning

confidence: 99%

Section: B Radiation Hardening By Designmentioning

confidence: 99%