Design and Analysis of a Low Power High-Performance GDI based Radix 4 Multiplier Using Modified Booth Wallace Algorithm

Mukherjee, Biswarup; Ghosal, Aniruddha

doi:10.1109/edkcon.2018.8770494

Cited by 6 publications

(10 citation statements)

References 9 publications

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“…• Finally addition operation is done for all the partial products to get the final result. In our previous communication [24] it has been found that the encoder circuit has a critical path delay on producing 2X output. To reduce the latency of the critical path, cyclic methodology has been introduced to generate 2X output.…”

Section: Radix-4 Modified Booth's Algorithmmentioning

confidence: 97%

“…In our previous communication [24] various types of multiplier architectures and their merits and demerits have been discussed. It was found that the GDI based modified Booth Wallace tree multiplier is the most power and delay efficient compared to other available designs.…”

Section: The Multiplier Unitmentioning

confidence: 99%

“…The circuit shown in figure 4 consists of two quantities of three transistors based XOR gates [26] and a two transistors based GDI F1 function [5]. Compared to previous GDI encoder design [24], which was made with nine transistors and two inverters (additional four transistors), the circuit shown in figure 4 has only eight transistors.The CCGDI based Booth encoder transient responses are shown below in figure 5. The simulation environment is set as detailed in table 2.…”

Section: Radix-4 Modified Booth's Algorithmmentioning

confidence: 99%

See 2 more Smart Citations

Design of a low power, double throughput cyclic combinational gate diffusion input based radix-4 MBW multiplier and accumulator unit for on-chip RISC processors of MEMS sensor

Mukherjee

Ghosal

2019

J. Micromech. Microeng.

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Modern microsystems based on sensor specific structures have robust on-chip digital signal processors to process the input signals. In order to improve the robustness of the system, on-chip processor circuitry has to be fabricated in limited areas with low latency and low power consumption. In this paper, a new technique for implementing low-power, high performance multiplier and accumulator (MAC) unit has been introduced for on-chip microelectromechanical systems applications. Based on cyclic combinational gate diffusion input technique, the proposed MAC unit is designed using Radix-4 modified Booth Wallace multiplier architecture and can operate up to 100 MBps of input data acquisition rate. Our proposed design is made of single threshold voltage transistors which employ low latency and reduced power consumption and less complexity in physical design. CAD tool based simulation at Generic 250 nm technology and comparison between proposed design with other available designs shows that the proposed design is better than many other designs for similar range of operation. The proposed design has an average power consumption of 98.8 mw and propagation delay of 6.8 ns at input bit rate 100 MBps for 16 bit operands.

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Section: Radix-4 Modified Booth's Algorithmmentioning

confidence: 97%

Section: The Multiplier Unitmentioning

confidence: 99%

Section: Radix-4 Modified Booth's Algorithmmentioning

confidence: 99%

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Design of a low power, double throughput cyclic combinational gate diffusion input based radix-4 MBW multiplier and accumulator unit for on-chip RISC processors of MEMS sensor

Mukherjee

Ghosal

2019

J. Micromech. Microeng.

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show abstract

“…The Radix-4 algorithm is an efficient way to increase the multiplication efficiency because it divides the multiplier into overlapping groups. Each group with three adjacent bits, which means there are eight states and according to the adjacent three bits of multiplier, the modified Booth's algorithm can produce the appropriate coefficient (𝑀 𝑖 ), in which 𝑀 𝑖 has five possible values (±1, ±2 𝑜𝑟 0); these coefficients have recoded the multiplicand, as depicted in TABLE 1 [6]. The advantage of this algorithm is that the partial product can be reduced by half.…”

Section: Modified (Radix-4) Booth's Multiplication Algorithmmentioning

confidence: 99%

“…D. Nandan et al, obtained a total power reduction of about (39 %) by using their proposed iterative logarithmic multiplier (ILM) technique based on Mitchell's algorithm with leading one detector (LOD) and smooth pipelined technique [5]. In [6], the Gate Diffusion technique on various architecture of multipliers is proposed. The total power optimization was (35 %) of the proposed design relative to other designs.…”

Section: Introductionmentioning

confidence: 99%

Power Optimization of Binary Multiplier Based on FPGA

Nasser¹,

Hashim²

2021

ETJ

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Low power dynamic voltage scaling and CCGDI based Radix-4 MBW multiplier using parallel HA and FA based counters for on-chip filter applications

Mukherjee

Ghosal

2020

Sādhanā

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Design and Analysis of a Low Power High-Performance GDI based Radix 4 Multiplier Using Modified Booth Wallace Algorithm

Cited by 6 publications

References 9 publications

Design of a low power, double throughput cyclic combinational gate diffusion input based radix-4 MBW multiplier and accumulator unit for on-chip RISC processors of MEMS sensor

Design of a low power, double throughput cyclic combinational gate diffusion input based radix-4 MBW multiplier and accumulator unit for on-chip RISC processors of MEMS sensor

Power Optimization of Binary Multiplier Based on FPGA

Low power dynamic voltage scaling and CCGDI based Radix-4 MBW multiplier using parallel HA and FA based counters for on-chip filter applications

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