Design and Analysis of a Mesh-based Wireless Network-on-Chip

Abstract

Network-on-chip (NoC) architecture is regarded as a solution for future onchip interconnects. However, the performance advantages of conventional NoC architectures are limited by the long latency and high power consumption due to multi-hop long-distance communication among processing elements. To solve these limitations, we employed on-chip wireless communication as express links for transferring data so that transfer latency can be reduced. A hybrid NoC architecture utilizing both wired and wireless communication approaches is proposed in this paper. We also devised a deadlock-free routing algorithm that is able to make efficient use of the incorporated wireless links. Moreover, simulated annealing optimization techniques were applied to find optimal locations for wireless routers. Cycle-accurate simulation results showed a significant improvement in transfer latency. Area and power consumption analysis demonstrates the feasibility of our proposed NoC architecture.

Proposing an optimal structure for the architecture of wireless networks on chip

“…Three-dimensional integration [14], optical interconnections [3] and WLs [6,7,10,11,15,16] are all methods for communicating between on-chip cores which aim to reduce latency and power consumption in NOC. Several studies have been conducted on the structure and routing algorithm related to ONoC.…”

“…In the paper, wherever antenna is mentioned, it refers to the WRs. In [7], the areas of BRs and WRs were estimated to be 0.108 and 0.175 mm 2 respectively. The comparison of the area of WRs with that of conventional processing elements (PEs) like ARM11MPCore [8] and PowerPC 405 processor [9] (which have been estimated to be 0.938 and 1.4 mm 2 in 65 nm technology respectively) indicates that it is sensible to use WRs in the architecture of WiNoC [7].…”

“…In this paper, the results of some previous works [7,10,11] were used and it was assumed that the center of each subnet can be considered as a potential location for the placement of antenna. Then, new factors will be proposed, a new cost function will be defined and algorithms simulated annealing (SA) [12] and genetic algorithm (GA) [13] will be used; using these, an attempt was made to allocate the PEs with the highest demand levels to the closest active antenna with regard to the defined cost.…”

High-performance adaptive hybrid wireless NoC architecture based on improved congestion measurement

“…Despite its many advantages, the drawbacks on high latency and power consumption, however, seriously hinder the further performance enhancement of multicore SoC with the increasing complexity [1]. On the one hand, nice topologies (e.g.…”

“…More recently, the Wireless NoC (WiNoC) has been proposed as a promising solution by integrating miniaturized on-chip antennas and transceivers to enable intra-chip wireless interconnection and communication [1,3,4], wherein the multihop wired links have been replaced by single-hop long-range wireless links to solve the wiring and performance limitations radically. Although the WiNoC architecture using all wireless links with UWB technology has been explored to transfer data between different nodes [5], excessive wireless nodes cause high power consumption and area overhead.…”