Design and Analysis of 7nm FinFET Full Custom Standard Cell Library using ASAP7 PDK

Lakshmanan, Anirudh; Mishra, Gaurav Kumar; Ravi, T.; N, Prashanth Srinivas

doi:10.1109/iccmc53470.2022.9753795

Cited by 3 publications

(2 citation statements)

References 14 publications

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“…Current research directions for standard cell libraries include advanced technology, lower dimensions, low-power, and radiation protection design. In advanced design technologies, Lakshmanan et al [6] have constructed a fully customized standard cell library for 7-nanometer FinFET technology. Additionally, Yang et al [7] have employed advanced MOL (Middle-of-Line) techniques to achieve the design of a standard cell library for 3-nanometer process technology.…”

Section: Introductionmentioning

confidence: 99%

Standard cell library design for edge computing chips

Lei,

Tang

2024

J. Phys.: Conf. Ser.

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With the rapid development of big data, IoT, and other technologies, edge computing has emerged, and the core of edge computing is the edge computing chip. To meet the rapidly growing data computing speed and data computing volume and taking into account the short design cycle and low cost, this paper proposes a standard cell library for designing edge computing chips based on the PDK of 0.13 μm SOI process. Compared with the existing edge computing chips that operate at 100 MHz, the edge computing chip designed with this cell library can operate at 1 GHz. The design process includes selecting cell types and heights for the cell library, designing and drawing circuit logic and layout, extracting characteristic parameters of the cell library, and verifying the cell functions. The validation results show the designed cell can operate at 1 GHz with low delay. Compared with a commercial device, the designed device has a higher operating frequency and realizes a good balance between area and power consumption, and the standard cell library has a good application prospect.

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Section: Introductionmentioning

confidence: 99%

Standard cell library design for edge computing chips

Lei,

Tang

2024

J. Phys.: Conf. Ser.

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“…During the chip design process, the foundry provides specific data and script files in the Electronic Design Automation (EDA) tool, as the PDK library used by the designer contains details about the semiconductor process. This enables design engineers to quickly create chips using the PDK [2]. A PDK typically consists of symbols, the Component Description Format (CDF), parameterized cells (PCells), the SPICE simulation model, the physical verification rule file (PVRule), and other components [3].…”

Section: Introductionmentioning

confidence: 99%

From Netlist to Manufacturable Layout: An Auto-Layout Algorithm Optimized for Radio Frequency Integrated Circuits

et al. 2023

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Layout stitching is a repetitive and tedious task of the radio frequency integrated circuit (RFIC) design process. While academic research on layout splicing algorithms mainly focuses on analog and digital circuits, there is still a lack of well-developed algorithms for RFICs. An RFIC system usually has a symmetrical layout, such as transmitter and receiver components, low-noise amplifier (LNA), an SPDT switch, etc. This paper aims to address this gap by proposing an automated procedure for the layout of RFICs by relying on the basic device/PCell structure based on the interconnection among circuit topologies. This approach makes the in-series generation of layouts and automatic splicing based on circuit logic possible, resulting in superior stitching performance compared with related modules in Advanced Design System. To demonstrate the physical application possibilities, we implemented our algorithm on an LNA and a switch circuit.

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