Design analysis of XOR (4T) based low voltage CMOS full adder circuit

Wairya, Subodh; Singh, Garima; Vishant,; Nagaria, R. K.; Tiwari, Sudarshan

doi:10.1109/nuicone.2011.6153275

Cited by 35 publications

(25 citation statements)

References 14 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Recreation comes about uncover that the composed circuits display bring down power delay product (PDP) and more power effectiveness and quicker when contrasted with the accessible full adder circuits having low value of voltage. The outline was actualized on UMC 0.18μm processing models when implemented on Cadence Virtuoso Schematic Composer tool at 1.8 V single finished voltage supply and recreations are completed on Specter S. [2] M.Aguirre-Hernandez et al (2011)We exhibit two rapid and low powered full-adder cells composed with an option inner logic structure and pass logic transistor rationale styles that prompt have a decreased power-delay product .We did an examination against other full-adders uncovered as having a low PDP, to the extent speed, control usage and zone. All the full-adders were formed with a 0.18-μm CMOS advancement, and were had a go at using a total test bench that allowed to gage the current taken from the full-adder inputs, other than the current gave from the power-supply.…”

Section: Literature Surveymentioning

confidence: 99%

A Study of Hybrid Full Adder for Low Power and High Speed Applications

2017

IJAERD

View full text Add to dashboard Cite

ABSTRACT-This paper present a review on the study of different logic style of full adders and taking positive aspects of these design style to form a hybrid for low power consumption and minimum propagation delay .In this paper our main focus is to find out the module of full adder which consume more power and then reducing the transistor count. so that it can be used in many applications like mobile phones ,PDA, laptop etc .as full adder is basic building block of various circuits.

show abstract

Section: Literature Surveymentioning

confidence: 99%

A Study of Hybrid Full Adder for Low Power and High Speed Applications

2017

IJAERD

View full text Add to dashboard Cite

show abstract

“…1(b)]. Various XOR/XNOR topologies have already been reported in [7] and [12]- [14]. The XOR/XNOR reported in [12]- [14] uses four transistors but at the cost of low logic swing.…”

Section: A Modified Xnor Modulementioning

confidence: 99%

Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit

Bhattacharyya

Kundu

Ghosh

et al. 2015

IEEE Trans. VLSI Syst.

230

View full text Add to dashboard Cite

In this paper, a hybrid 1-bit full adder design employing both complementary metal-oxide-semiconductor (CMOS) logic and transmission gate logic is reported. The design was first implemented for 1 bit and then extended for 32 bit also. The circuit was implemented using Cadence Virtuoso tools in 180-and 90-nm technology. Performance parameters such as power, delay, and layout area were compared with the existing designs such as complementary pass-transistor logic, transmission gate adder, transmission function adder, hybrid pass-logic with static CMOS output drive full adder, and so on. For 1.8-V supply at 180-nm technology, the average power consumption (4.1563 µW) was found to be extremely low with moderately low delay (224 ps) resulting from the deliberate incorporation of very weak CMOS inverters coupled with strong transmission gates. Corresponding values of the same were 1.17664 µW and 91.3 ps at 90-nm technology operating at 1.2-V supply voltage. The design was further extended for implementing 32-bit full adder also, and was found to be working efficiently with only 5.578-ns (2.45-ns) delay and 112.79-µW (53.36-µW) power at 180-nm (90-nm) technology for 1.8-V (1.2-V) supply voltage. In comparison with the existing full adder designs, the present implementation was found to offer significant improvement in terms of power and speed.Index Terms-Carry propagation adder, high speed, hybrid design, low power.

show abstract

“…In Fig. 1 (a), a 3-input AND/XOR gate is implemented by cascading one NAND gate and one XOR gate in complementary CMOS structure [4][5], which consists of a pull-up PMOS network and a pull-down NMOS network. As a result, the gate circuit has a symmetrical structure and operates with full output voltage swing, but it requires significant transistors and high power consumption.…”

Section: Published 3-input And/xor Gatesmentioning

confidence: 99%

A Novel 3-Input AND/XOR Gate Circuit for Reed-Muller Logic Applications

2016

View full text Add to dashboard Cite

Abstract. 3-input AND/XOR is the basic complex gate of Reed-Muller logic. Low energy consumption is important for Reed-Muller logic circuit implementation. Against the drawbacks of the published gate-level and transistor-level 3-input AND/XOR gate design in power and power delay product (PDP), a low energy consumption 3-input AND/XOR gate is proposed by employing multi-rails and hybrid-CMOS techniques to improve its speed and short the signal transimission path. Under 55nm CMOS process, post-simulations in different process corners are carried out by using HSPICE and compared with the published circuits. Simulation results show that the proposed circuit has advantages over published designs. For typical process corners, the improvement of the proposed circuit can be up to 27.21%, 19.23% and 35.39%, respectively, in terms of power, delay and power delay product.

show abstract

Design analysis of XOR (4T) based low voltage CMOS full adder circuit

Cited by 35 publications

References 14 publications

A Study of Hybrid Full Adder for Low Power and High Speed Applications

A Study of Hybrid Full Adder for Low Power and High Speed Applications

Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit

A Novel 3-Input AND/XOR Gate Circuit for Reed-Muller Logic Applications

Contact Info

Product

Resources

About