Design &amp;amp; study of a low power high speed full adder using GDI multiplexer

Mukherjee, Biswarup; Ghosal, Aniruddha

doi:10.1109/retis.2015.7232924

Cited by 15 publications

(2 citation statements)

References 5 publications

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“…The considerably low average power consumption of the GDI approach is due to the lesser number of transistors used in the GDI approach as compared to the PTL approach. This finding supported previous work which also demonstrated that the full adder using a MUX with a GDI approach has lower average power consumption than a conventional CMOS full adder [14].…”

Section: Resultssupporting

confidence: 91%

Simulation and Characterization of Carbon Nanotube-based 2:1 Multiplexer Electrical Properties

Ying,

Johari

2023

J. Phys.: Conf. Ser.

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This paper reports on using simulation to characterize a Carbon Nanotube (CNT) based 2:1 multiplexer (MUX). This study aimed to evaluate the electrical properties, particularly the propagation delay, average power consumption, Power-Delay Product (PDP), and Energy-Delay Product (EDP). Different design approaches namely conventional CMOS, Pass Transistor Logic (PTL) approach, and Gate Diffusion Input (GDI) were adopted. The voltage supply (VDD) and diameter of the CNT are varied to see the effect on the electrical properties. The simulation was carried out using HSPICE. Through simulation, it is found that the GDI approach used the least number of transistors followed by PTL and CMOS. The calculation of the propagation delay exhibits a substantial improvement of more than 95% using the GDI approach. The average power consumption shows a 55.30% and 35.16% reduction when compared to CMOS and PTL respectively. The PDP demonstrates an improvement of more than 95% when compared with conventional CMOS and PTL approaches. The same trend of observation is also achieved for EDP. The variation of the VDD and chirality has a markable effect on the propagation delay and average power consumption. This is a preliminary attempt to evaluate the performance of CNT implementation in MUX. The outcome can become the guideline for engineers working in circuit design using emerging materials for future nanoelectronics applications.

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Section: Resultssupporting

confidence: 91%

Simulation and Characterization of Carbon Nanotube-based 2:1 Multiplexer Electrical Properties

Ying,

Johari

2023

J. Phys.: Conf. Ser.

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“…The variety of the design on a full adder is retrieved and compared from the other writers or authors that experiments with the same topics. [5] had designed a low power full adder high speed full adder that have better performance than the conventional full adder. [6] demonstrated their quaternary full adder designs which also provides positive results from the performance of their full adder design.…”

Section: Literature Reviewmentioning

confidence: 99%

Design and Analysis of Full Adder Using 0.6 Micron CMOS Technology

Fei¹,

Rahman²,

Subramaniam³

et al. 2023

Malaysian J. Sci. Adv. Tech.

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The design of a full adder involves the use of logic gates so that the design can convert 8 inputs to create a byte-wide adder and to force the carry bit to the other adder. However, the uses of multiplexers to replace the logic gates in the construction of the full adder is proven to be possible due to the function of the multiplexers to act as the digital switch in the system that provides the flow of digital information from multiple inputs into an output. This research aims to explore the possibility of implementing the multiplexers into the design of the full adder and to analyse the different possible full adder design using the multiplexers. Using the multiplexers also allows for fewer logic gates to be used in the design of the full adder, which reduces the overall area coverage of the full adder. However, adding multiplexers does not make a complete adder more efficient and may slow it down. Thus, this article compares a conventional full adder with logic gates, a full adder with two 2:1 multiplexers, and a full adder with six 2:1 multiplexers in terms of power usage, time delay of the Sum and Carry outputs, and technology (0.6 μm).

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