Design &amp;amp; implementation of MQAM based IEEE 802.15.4/ZigBee Tranceiver using HDL

Supare, Vivek P.; Sayankar, Bharati B.; Agrawal, Pankaj

doi:10.1109/icstm.2015.7225460

Cited by 5 publications

(3 citation statements)

References 3 publications

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“…On a 65 nm CMOS process, the design utilizes 22,309 cells and consumes 0.197 mW of power. Supare et al [16] present the M-ary quadrature amplitude modulation (MQAM) based Zigbee transceiver module on the FPGA platform. The transmitter and receiver use a 2.4 GHz frequency band for MQAM modulation operation.…”

Section: Introductionmentioning

confidence: 99%

Design of an efficient binary phase-shift keying based IEEE 802.15.4 transceiver architecture and its performance analysis

Raj

Gowda

2022

IJECE

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<span lang="EN-US">The IEEE 802.15.4 <a name="_Hlk109306810"></a>physical layer (PHY) standard is one of the communication standards with wireless features by providing low-power and low-data rates in wireless personal area network (WPAN) applications. In this paper, an efficient IEEE 802.15.4 digital transceiver hardware architecture is designed using the binary phase-shift keying (BPSK) technique. The transceiver mainly has transmitter and receiver modules along with the error calculation unit. The BPSK modulation and demodulation are designed using a digital frequency synthesizer (DFS). The DFS is used to generate the in-phase (I) and quadrature-phase (Q) signals and also provides better system performance than the conventional voltage-controlled oscillator (VCO) and look up table (LUT) based memory methods. The differential encoding-decoding mechanism is incorporated to recover the bits effectively and to reduce the hardware complexity. The simulation results are illustrated and used to find the error bits. The design utilizes less chip area, works at 268.2 MHz, and consumes 108 mW of total power. The IEEE 802.15.4 transceiver provides a latency of 3.5 clock cycles and works with a throughput of 76.62 Mbps. The bit error rate (BER) of 2×10-5 is achieved by the proposed digital transceiver and is suitable for real-time applications. The work is compared with existing similar approaches with better improvement in performance parameters.</span>

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Section: Introductionmentioning

confidence: 99%

Design of an efficient binary phase-shift keying based IEEE 802.15.4 transceiver architecture and its performance analysis

Raj

Gowda

2022

IJECE

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“…In this manuscript, the 802. 15 FPGA based ZigBee baseband modem designed by muni et al [11] as per IEEE 802.15.4 standard. The design includes a transmitter with half-sine pulse shaping along with Receiver.…”

Section: Introductionmentioning

confidence: 99%

“…The ZigBee baseband transmitter and Receiver works based 802.15.4 standard. Supare et al [15] presented the Digital QAM based ZigBee modem design using HDL. They implemented on FPGA, which includes FIR filter, SIPO-PISO converters, up-down samplers, and Chip encoder-decoders.…”

Section: Introductionmentioning

confidence: 99%

Design and Implementation of 802.15.4 Transceiver for Wireless Personal Area Networks (WPANs) on FPGA

S.P*,

B.S

2020

IJITEE

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The IEEE 802.15.4 standard provides mainly accessing, monitoring, and controlling capability of the Wireless devices. This standard supports short-range wireless communications and Low Rate (LR) - Wireless Personal Area Networks (WPANs). This manuscript presents the fully integrated digital 802.15.4 Transceiver, which suitable to ZigBee Device Standard at 2.4GHz range. The 802.15.4 Transceiver design includes an 8-bit input data sequence mapped to lower and Upper Symbols followed by Chip-sequence conversion as per the IEEE standard. The chip sequences are mapped separately as even and odd sequences used for the Offset-QPSK Modulation. The chip synchronization achieved by using a proper clocking mechanism on the receiver side. The 802.15.4 Transceiver design is implemented on Artix-7 FPGA using Xilinx Environment. The hardware constraints like Area (Slices), Frequency, and Power are analyzed. The proposed work also compared with existing similar approaches with more significant improvements in chip area and Power.

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