Deriving Signal Transition Graphs from Behavioral Verilog HDL

Blunno, I.; Lavagno, Luciano

doi:10.1007/978-1-4757-3143-9_8

Cited by 1 publication

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References 14 publications

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“…Graph specification is not straightforward to recognize the functionality of system, error prone and difficult to debug, so for complex system, it is too large and tedious to manage. Thereafter, high-level language based description approaches are proposed [64,65]. Employing existing HDL language to specify async circuits from the system level not only mask the complexity of systems, but also enable off-the-shelf commercial EDA tools to verify functionality, which is definitely a promising interface with current sync design flow.…”

Section: Logic Synthesismentioning

confidence: 99%

Design methodologies for robust and low-overhead asynchronous quasi-delay-insensitive digital systems

Zhou¹

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In the past decades of electronic circuit designs, the synchronous-logic (sync) is the main de-facto design approach for digital systems. This is largely due to its synchronization to a global clock signal (or its variants thereof) which simplifies the data transfer. Nevertheless, designing digital circuits and systems based on sync approach is becoming more challenging due to the increase in process, voltage and temperature (PVT) variations in the deep submicron fabrication process. An alternative design approach which is based on the asynchronous-logic (async), is

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Section: Logic Synthesismentioning

confidence: 99%

Design methodologies for robust and low-overhead asynchronous quasi-delay-insensitive digital systems

Zhou¹

View full text Add to dashboard Cite

show abstract

Deriving Signal Transition Graphs from Behavioral Verilog HDL

Cited by 1 publication

References 14 publications

Design methodologies for robust and low-overhead asynchronous quasi-delay-insensitive digital systems

Design methodologies for robust and low-overhead asynchronous quasi-delay-insensitive digital systems

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