Derivation of multilevel voltage source converter topologies

Yuan, Xibo

doi:10.1109/iecon.2016.7794020

Cited by 14 publications

(33 citation statements)

References 37 publications

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“…All these applications are possible due to the ability of the MLI to provide a better output voltage with a more sinusoidal shaped waveform, improved efficiency due to the lower switching frequency operation of switches, lower blocking voltage requirement with reduced dv/dt and improved electromagnetic compatibility. Another positive impact of MLI is the reduction of the filter size and cost due to the reduced amount of harmonics at the output [1]- [7].…”

Section: Introductionmentioning

confidence: 99%

Optimal Design of a New Cascaded Multilevel Inverter Topology With Reduced Switch Count

et al. 2019

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Multilevel inverters (MLIs) are a great development for industrial and renewable energy applications due to their dominance over conventional two-level inverter with respect to size, rating of switches, filter requirement, and efficiency. A new single-phase cascaded MLI topology is suggested in this paper. The proposed MLI topology is designed with the aim of reducing the number of switches and the number of dc voltage sources with modularity while having a higher number of levels at the output. For the determination of the magnitude of dc voltage sources and a number of levels in the cascade connection, three different algorithms are proposed. The optimization of the proposed topology is aimed at achieving a higher number of levels while minimizing other parameters. A detailed comparison is made with other comparable MLI topologies to prove the superiority of the proposed structure. A selective harmonic elimination pulse width modulation technique is used to produce the pulses for the switches to achieve high-quality voltage at the output. Finally, the experimental results are provided for the basic unit with 11 levels and for cascading of two such units to achieve 71 levels at the output. INDEX TERMS Basic unit, cascaded inverter, multilevel inverter (MLI), selective harmonic elimination, SHEPWM, optimization, reduce switch count. II. ANALYSIS AND DESCRIPTION OF PROPOSED MULTILEVEL TOPOLOGY A. BASIC UNIT OF PROPOSED TOPOLOGY

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Section: Introductionmentioning

confidence: 99%

Optimal Design of a New Cascaded Multilevel Inverter Topology With Reduced Switch Count

et al. 2019

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“…For some multilevel topologies, the switching pattern in Fig.1 (a) is not enough for certain control purposes. For example, the switching pattern in Fig.1 (a) is not sufficient to regulate the dc-link capacitor voltages for four-level or fivelevel NPC converters at high modulation indexes or high power factors [17]. To solve this problem, the switching pattern in Fig.1 (b) was introduced where there are four switching transitions and three voltage levels are used instead of two in each switching period.…”

Section: Imentioning

confidence: 99%

A Fast Multilevel SVPWM Method Based on the Imaginary Coordinate With Direct Control of Redundant Vectors or Zero Sequence Components

Yuan

Gao

2020

IEEE Open J. Ind. Electron. Soc.

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“…Recently, the research trend is steered towards the modification of the Hbridge by module configurations with higher compactness and less switch count. The developed module topologies are able to generate more voltage levels while at the same time offer higher efficiency [18,19]. The switched DC sources concept from CHB is mostly retained as it remains a popular approach in generating multiple voltage levels [20].…”

Section: Introductionmentioning

confidence: 99%

Cascaded single-phase, PWM multilevel inverter with boosted output voltage

Nnadi¹,

Oti²,

Odeh³

2020

Nig. J. Tech.

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Splitting of a dc voltage source with two capacitors has been the approach in generating 5-level output voltage with single- and three-phase full-bridge circuits and added bidirectional switch. Associated with this configuration is the problem of voltage imbalance between the splitting capacitors. In addition, the inverter output voltage magnitude is obviously limited to the value of the split input voltage source. Presented in this paper is a unit topology for single-phase 5-level multilevel inverter, MLI. It simply consists of a full-bridge circuit, a capacitor, charge-discharge unit and a dc source. The charge-discharge unit with the capacitor is the interface between the full-bridge and the dc source. The proposed unit cell can generate a 5-level output voltage waveform whose peak value is twice the input voltage value. For higher output voltage level, a cascaded structure of the developed unit cell is presented. Comparing the proposed inverter with CHB inverter and some recent developed MLI topologies, it is found that the proposed inverter configuration generates higher output voltage value, at reduced component-count, than other topologies, for a specified number of dc input voltages. For two cascaded modules, simulation and experimental verifications are carried out on the proposed inverter topology for an R-L load. Keywords: Cascaded multilevel, Inverter, total harmonic distortion, topologies, waveform

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Derivation of multilevel voltage source converter topologies

Cited by 14 publications

References 37 publications

Optimal Design of a New Cascaded Multilevel Inverter Topology With Reduced Switch Count

Optimal Design of a New Cascaded Multilevel Inverter Topology With Reduced Switch Count

A Fast Multilevel SVPWM Method Based on the Imaginary Coordinate With Direct Control of Redundant Vectors or Zero Sequence Components

Cascaded single-phase, PWM multilevel inverter with boosted output voltage

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