Dependability evaluation of integrated circuits at design time against laser fault injection

Abstract

Laser fault injection has been proved to be a useful tool for attacks on integrated circuits. Transistors hit by a pulse of photons causes them to conduct transiently, thereby introducing transient logic errors, such as register value modifications, memory dumping, and so on. Attackers can make use of this abnormal behavior and extract sensitive information that the devices try to protect. This paper demonstrates laser fault injection attacks on very-large-scale integration circuits in a semi-invasive way for the purpose of validating fault tolerant design and performance. Then, the paper presents a simulation methodology to evaluate the dependability of the integrated circuit design against laser fault injection attacks at design time. This simulation methodology involves exhaustively scanning the layout, incorporating the exposed cells into a circuit simulator, and examining the response of the circuit in detail. Experiments conducted on the same test chip spot the same vulnerabilities, thus indicating the validity of the proposed simulation methodology.