2019 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS) 2019
DOI: 10.1109/rtas.2019.00037
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Denial-of-Service Attacks on Shared Cache in Multicore: Analysis and Prevention

Abstract: In this paper we investigate the feasibility of denialof-service (DoS) attacks on shared caches in multicore platforms. With carefully engineered attacker tasks, we are able to cause more than 300X execution time increases on a victim task running on a dedicated core on a popular embedded multicore platform, regardless of whether we partition its shared cache or not. Based on careful experimentation on real and simulated multicore platforms, we identify an internal hardware structure of a nonblocking cache, na… Show more

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Cited by 46 publications
(38 citation statements)
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References 39 publications
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“…For example, we observed more than 100X slowdown (two orders of magnitudes) using a linked-list iteration task on the same computing platform used above, even after we partition core as well as the shared cache among the tasks. Similar degrees of timing impacts of interference have been reported in recent empirical studies on contemporary embedded multicore platforms [7], [8], [51], [52], [57].…”
Section: Motivationsupporting
confidence: 80%
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“…For example, we observed more than 100X slowdown (two orders of magnitudes) using a linked-list iteration task on the same computing platform used above, even after we partition core as well as the shared cache among the tasks. Similar degrees of timing impacts of interference have been reported in recent empirical studies on contemporary embedded multicore platforms [7], [8], [51], [52], [57].…”
Section: Motivationsupporting
confidence: 80%
“…While these shared resource partitioning techniques can reduce space conflicts of some shared resources, hence beneficial for predictability, but they are not enough to guarantee strong time predictability on COTS multicore platforms because there are too many hardware resources (e.g., cache MSHRs, DRAM controller buffers, etc.) that have profound impact on task timing [8], [51], but are unpartitionable and out of control of software.…”
Section: Related Workmentioning
confidence: 99%
“…As in prior work [24], [3], we are interested in evaluating commodity hardware using a regular (i.e. non-real-time) operating system, as this is a realistic usage scenario for early evaluation of COTS processors.…”
Section: Measuring Interference Reliablymentioning
confidence: 99%
“…We attempted to reproduce the highest slowdowns reported in recent interference work by Bechtel and Yun [3]: namely, that their BwWrite enemy program can cause a slowdown of more than 300× on a synthetic memory-intensive piece of software (on a Raspberry Pi 3 B chip). The architectural intuition behind these results is that the BwWrite program exploits the internal structure of non-blocking shared caches by filling the miss-status holding register and write-back buffer.…”
Section: Measuring Interference Reliablymentioning
confidence: 99%
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